Recent Graduates

• Dan Adler: A Parallel Switch-Level Circuit Simulator.
• Abhishek Bisaria: Frequency Spectrum Testing for Mixed Digital/Analog Circuits.
• Dan Brasen: Full-Custom Macro Cell Floorplanning and Placement Under Timing Constraints.
• Dr. Tapan Chakraborty: Delay Fault Test-Pattern Generation for Random Logic State Machines.
• Dr. Srimat Chakradhar: Neural Network Models for Test-Pattern Generation.
• Andrew Chang: An Implementation of Constrained Quadratic 0-1 Programming for Automatic Test Pattern Generation for VLSI Circuits.
• Shweta Chary:
• Xinghao Chen: Full-Custom Layout Area and Aspect Ratio Estimation.
• Dr. Xinghao Chen: Sequential Circuit Automatic Test Generation.
• Carolina Cooper: Automatic Switch-Level Test Generation Using Energy Minimization.
• Kunal Dave:
• Vivek Gaur: A Transitive Closure Algorithm for Redundant Fault Identification.
• Dr. Marwan Gharaybeh: Path Delay Fault Classification, Testing, and Fault Simulation.
• Pomeli Ghosh: Transistor Stuck-Open Fault Test Generation for Switch-Level Circuits Using Energy Minimization Techniques.
• Dr. John Giraldi: Search Space Equivalence for Combinational Redundancy Identification and Test-Pattern Generation.
• Dr. Keerthinarayan Heragu: Approximate and Statistical Methods to Compute Delay Fault Coverage.
• Madhu Iyer: Effect of Noise on Analog Circuit Testing.
• Qing Lin: Efficient Techniques for a Transitive Closure-Based Test Generation Algorithm.
• Sameer Mangalampalli: Response compacters for analog Built-In Self-Test.
• Vishal Mehta:
• Sanjay Mohan: Code Transition Delay Fault Models for A/D Converter Testing.
• Lakshminarayana Pappu: Statistical Path and Gate Delay Fault Coverage Estimation in Sequential Circuits.
• Karthikeya Parameswaran:
• Sandip Parikh: Automatic CAD Tool Execution in the Ulysses II CAD Framework.
• Carlos Parodi: Exact Non-Enumerative Path-Delay Fault Simulation of Sequential Circuits.
• Ganapathy Parthasarathy: Delay Fault Built-In Self-Test and Partial-Scan Insertion for Sequential Circuits.
• Tejaswi Raja: Linear Programming algorithms for low-power design and critical path acceleration.
• Dr. Tejaswi Raja: Linear Programming algorithms for low-power design and critical path acceleration.
• Rajesh Ramadoss: Test Generation for Mixed-Signal Devices Using Signal Flow Graphs.
• Dr. Lan Rao: IDDQ Testing for Excessive Chip Current Faults.
• Aditya Sathe: Automatic Test-Pattern Generation for Analog Capacitive Coupling Faults using Variable Time-Delay Logic Simulation.
• Imtiaz Shaik: Robust Built-In Self-Testing for Circuit Delay Faults.
• Dr. Imtiaz Shaik: Built-In Self-Test for Delay Faults.
• James Sienicki: Graphical Methodology Language for CAD Frameworks.
• Dr. James Sienicki: Test Generation on Parallel Computers Based on Order Statistics.
• Krishna Upadhyayula: Test Pattern Generation Using Spectral Built-In Self-Test (BIST).
• Joseph Williams: K-Tree Circuit Partitioning.

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