VLSI Design And Testing Inventions

• EST - short for Equivalent STate Hashing Algorithm - a Learning Algorithm for Redundancy Identification and Test Generation that was the fastest combinational test generator of its time.
• SEST, for Sequential EST - a single stuck-at fault gate-level Sequential Circuit Test Pattern Generator using the concept of Justification Decomposition Equivalence. This became IBM's standard sequential test generator in their TESTBENCH tool suite.
• MAE - an Efficient Module Area Estimator for standard-cell and full-custom VLSI Layouts using Probability Models. This area estimator is widely used at Intel.
• MHERTZ - one of the very first timing-driven full-custom floor planners. This became the basis for Compass Design Automation's floorplanning tool.
• REDUN - a REDUNdancy Viewing and Removing Program.
• A Neural Net Model for Combinational Test Generation.
• TRAN - A Transitive Closure Algorithm for Test Generation. This became the basis for NEC's standard test generators TRAN and SATURN that are used throughout NEC.
• A Transitive Closure Algorithm for Switch-level Test Generation for Digital Circuits.
• A Robust Built-In Self-Test hardware addition algorithm for Delay Faults - U.S. Patent # 5,422,891, 6/6/95.
• A Statistical Fault Coverage Estimator for Delay Faults.
• VNRSEST - Validatable Non-Robust SEST. This is the fastest known sequential test generator for path delay-faults.
• Mixed-Signal Analog/Digital Test Generation - U.S. Patent # 5,831,437, 11/3/98.
• Mixed-Signal Analog Test Generation Using Modified Nodal Anlysis - U.S. Patent pending.
• Partial-Scan Sequential Delay-Fault BIST - U.S. Patent pending.
• Path Status Graph for Path Delay-Fault Simulation. This tool has been transferred to Bell Laboratories for use on future SONET chips in telephone exchanges. - U.S. Patent # 6,131,181, 10/10/2000.
• Delay DNL - A Hardware Code Transition Delay Fault Response Compacter for Testing A/D Converters. - Invention Disclosure Filed.
• A New Redundant Fault Identification Algorithm Based on Implication Graphs and Transitive Closure Algorithms.
• A Spectral Testing Method that Reconfigures a Digital Circuit to Effectively Synthesize an Analog Test Waveform for the D/A Converter, Reconstruction Filter, and Analog Circuit Cascaded With It.
• A New Spectral Test Generation Method that Uses a Variable Time Delay Digital Fault Simulator and Analog Macromodels to Generate Tests for Capacitive Coupling Faults in High-Speed Digital Circuits.

To the current research

Up to the group home page