Nanotechnology VLSI Design & Test

The Nanotechnology VLSI Design and Testing group is an integral part of Center for Advanced Information Processing (CAIP), an Advanced Technology Center at Rutgers University . The Nanotechnology Group also participates in the Wireless Information Laboratory (WINLAB) of Rutgers. This page contains information about the Cadence design tools extensively used in classes and research programs in the Electrical and Computer Engineering Dept. at Rutgers. Students obtain practical experience in advanced electronics design using state-of-the-art CAD tools, computing and laboratory facilities, and access to the MOSIS foundry for prototyping of integrated circuits.

The 332:482, 332:578, 332:574, 332:479, 332:438, and 332:577 classes feature advanced design projects using the Cadence tools, and student chip designs are fabricated through the MOSIS foundry service with support from the MOSIS Educational Program (MEP).

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Contact Prof. Bushnell by

  • Snail-mail:
Prof. Michael Bushnell
CAIP Research Center
Rutgers University
96 Frelinghuysen Rd.

Piscataway, NJ 08854-8088
  • Email:
    bushnell@caip.rutgers.edu
  • Phone: (732)445-4854; Fax: (732)445-4775

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bushnell@caip.rutgers.edu; July 29, 2004