Homework Assignments, Spring 2001
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Homework 1: Introduction and ATE                 Due Feb 9, 2001
Problems 1.2, 1.4, 2.3 and 2.5

Homework 2: Economics, Yield and Fault Modeling  Due Feb 16, 2001
Problems 3.2, 3.6, 4.2, 4.5 and 4.11

Homework 3: Simulation                           Due Mar 2, 2001
Write a true-value logic simulation program for combinational circuits.
Represent signals by two-state (0,1) logic.  The inputs to the program
are: (1) an input vector file, (2) flat circuit description in the
Rutmod format, and (3) a user-supplied list of signals (default primary
outputs) for which simulated values are desired.  The output of the program
should be a table of signal values.  Use your program to verify the design
of a four-bit ripple-carry adder using the vectors of Table 5.1.  Execute
the following steps:
(a) Manually compute the output of each vector
(b) Run simulator to verify that your circuit produces correct outputs
(c) Diagnose a netlist encoding error - In the verified circuit, change one
    gate (e.g., replace AND by OR).  Starting from an incorrect PO, examine
    signal values until you locate the error.
Prepare a report (no longer than 5 pages) on program (algorithm, user manual),
and the results of (a), (b) and (c).  Program listing can be attached and
can be in addition to 5 pages.

Homework 4: Testability Measures                 Due Feb 23, 2001
Problems 6.3, 6.6 and 6.9

Homework 5: Combinational ATPG                   Due Feb 23, 2001
Problems 7.1, 7.3 and 7.7

Homework 6: Advanced Combinational ATPG          Due Mar 2, 2001
Problem 7.21

Homework 7: Sequential Circuit ATPG              Due Mar 9, 2001
Problems 8.5 and 8.19

Homework 8: Memory Test                          Due Mar 16, 2001
Problems 9.1, 9.2, 9.13 and 9.22

Homework 9: Analog Test                          Due Mar 25, 2001
Problems 10.3, 10.11, 10.14 and 11.5

Homework 10: Delay Test                          Due Apr 6, 2001
Problems 12.2 and 12.6

Homework 11: IDDQ Test                           Due Apr 13, 2001
Problem 13.2

Homework 12: Scan Design                         Due Apr 13, 2001
Problems 14.4, 14.8 and 14.9

Homework 13: BIST                                Due Apr 20, 2001
Problems 15.9 and 15.22