Rutgers University Electrical and Computer Eng. Dept. Cadence University Program Member

This page contains information only about the Cadence design tools extensively used in classes and research programs in the Electrical and Computer Engineering Dept. at Rutgers. Students obtain practical experience in advanced electronics design using state-of-the-art CAD tools, computing and laboratory facilities, and access to the MOSIS foundry for prototyping of integrated circuits.

The following courses make use of the Cadence system:

• Web Site for Rutgers University Introductory VLSI Design Courses 14:332:479 and 16:332:574

Introductory undergraduate and graduate Digital VLSI Design. Silicon models of information and signal processing functions. Structured design and parallelism. Microprocessor design and process scaling. The Cadence tools Schematic Composer, Virtuoso Layout Editor, Design Rule Checker, Dracula, Assura Circuit Extractor, Spectre Analog Simulator, Verilog-XL, and Silicon Ensemble are used. Students create layouts for their homework assignments using these tools. Schematic Composer is used for digital logic and switch-level schematic entry, and Verilog-XL and Spectre are used to simulate the schematics. Virtuoso and Silicon Ensemble are used to create the layouts, DRC and Dracula are used to check them, and Assura and Spectre are used to simulate them. In addition, teams of 4 to 7 graduate students use Cadence to create and simulate logic and switch-level schematics for a System-on-a-Chip, consisting of a microprocessor, a baseband or DSP processor, DRAM and SRAM memory, busses, and peripheral interfaces.

• Web Site for Rutgers University Course Capstone Design -- VLSI Design 14:332:480

Tool usage is the same as for 332:479. Teams of 4 to 7 undergraduate students use Cadence tools to create and simulate logic, switch-level, and analog schematics for a System-on-a-Chip, consisting of a microprocessor, a baseband or DSP processor, DRAM and SRAM memory, busses, and peripheral interfaces.

• Web Site for Rutgers University Deep Submicron VLSI Design Courses 14:332:482 and 16:332:578

Advanced deep submicron (DSM) VLSI Design. Berkeley BSIM V3 transistor models, models of dynamic, short circuit and leakage power, low-power logic families, advanced synchronous circuit design, DSM fabrication processes, low-power design, and robustness to process variations. Circuits for deep-submicron designs, deep-submicron coupling faults and testing, dual VT processes, and variable voltage supplies. Tool usage is the same as for 332:479. Undergraduate and Graduate students use Cadence tools to do their homework. Teams of 4 to 7 graduate students use Cadence tools to create and simulate a complete layout for a System-on-a-Chip (SoC), consisting of a microprocessor, a baseband or DSP processor, DRAM and SRAM memory, busses, and peripheral interfaces. It is quite common for the SoC to have 400 million transistors.

• Web Site for Rutgers University Course Analog and Low-Power Digital VLSI Design 16:332:577

Analog VLSI design and advanced low-power digital VLSI design course. Tool usage is the same as for 332:479, except that now students are also desiging analog VLSI circuits. The students will design combinational and sequential digital low-power circuit layouts using Cadence tools.  Also, each student will use Cadence tools to design the analog OP-AMP, the Gilbert Cell, and a personal analog circuit course project, which will be fabricated.

• Web Site for Rutgers University Course Testing of ULSI Circuits 16:332:576

Testing of VLSI circuits, including automatic test equipment, fault modeling, fault simulation, testability measures, automatic test pattern generation (ATPG) for digital, memory, and analog circuits, and design for testability, including scan insertion, built-in self-testing, JTAG boundary scan standards, and system test. Cadence tools Virtuoso, Schematic Composer, Verilog-XL, Assura, and Spectre are very occasionally used, when a student is doing a defect study of testing at the layout level.

The 332:482, 332:578, 332:574, 332:479, 332:480, and 332:577 classes feature advanced chip layout design projects using the Cadence tools, and student chip designs are fabricated through the MOSIS foundry service with support from the MOSIS Educational Program (MEP). The 332:576 course sometimes uses the Cadence tools to investigate novel testing ideas for VLSI chips.

VLSI Design and Testing Graduate Students and their Cadence tool Usage in Research Projects:

• Jeff Ayres: MS Completed. Developed Auto-Regressive, Moving-Average models of faults for built-in self-testing of linear and non-linear analog circuits. Used Cadence Schematic Composer and Spectre to simulate the circuits, and wrote an interface to Matlab using Ocean scripts in order to analyze fault models. This work appeared at VLSI Design 2007. Working at Lockheed-Martin.
• Sharanya Chandrasekar: MS Completed. Redesigned circuits for Low-Power consumption using a combination of VDD assignment, VT assignment, and retiming. Working at AMD.
• Aditya Jagirdar: MS student. Invented a new type of flip-flop that uses time redundancy and that can recover from crosstalk noise and/or crosstalk delay problems in 65 nm technology circuits (published at NATW 2006). Working at Conexant in Red Bank, NJ.
• Omar Khan: PhD student. Invented a spectral analysis procedure for built-in self-testing of digital circuits using Hadamard DSP matrices to analyze the digital frequencies at which the digital faults respond. He is now working on spectral analysis for testability insertion using Rademacher-Walsh matrices and using entropy analysis. This work appeared at NATW 2007 and will appear at ITC 2007. He does not use Cadence tools in his research.
• Dan Mazor: MS Completed. Has created single-electron nanotechnology devices in conjunction with a group of solid state physicists at the University of Canterbury in New Zealand. He investigated the fault models for defects in 20 to 60 nanometer feature size single-electron transistors (SETs). Published at Electronics in New Zealand conference, 2005 and at VLSI Design, 2007. Working at AMD.
• Roystein Oliveira: MS Completed. Has designed a new type of flip-flop that uses triple modular redundancy and that is resistant to the single event upsets that will plague 65 nm chip technology (published at NATW 2006). Working at AMD, Austin, TX.
• Rohit Pandey: MS Completed. Developed a novel combined FFT/Modified Walsh Transform/Discrete Cosine Transform baseband processor that can be used for 802.11 a/b/g, WiMAX, and other digital communications protocols for a cognitive radio. This work appeared at VLSI Design 2007. Does not use Cadence tools in his research. Working at Broadcom.
• Gagandeep Sandha: MS Completed. He has invented a new false path classifier for large digital circuits that uses an O(N) algorithm based on implication graphs. This work appeared at NATW 2007. Working at Qualcomm.
• Varadan Veeravalli Savulimedu: MS student. Working on designing a low-power, fault-tolerant microprocessor for medical applications in hospitals.
• Rajamani Sethuram: PhD Completed. He has invented a new type of sequential Automatic Test-Pattern Generator (ATPG) that uses 64 concurrent time frames represented simultaneously in an implication graph to generate shorter tests more rapidly for digital faults than prior ATPG algorithms could. He has invented a new way to compact combinational test patterns with scan shifting sequences by using new controllability and observability measures. The method drastically reduces test time and automatic test-pattern generation time for both structured ASIC and full-custom designs. This work appeared at VLSI Design 2007 and at NATW 2007. He does not use Cadence tools in his research. Working at Qualcomm.
• Hari Vijay Venkatanarayanan: PhD Completed. He has invented an autocorrelation and cross-correlation analysis method that allows us to take an arbitrary microprocessor or DSP core and transform it into a built-in analog waveform generator on a chip, when the core is cascaded with an untested Digital/Analog Converter (DAC). This method allows simultaneous and reliable testing of the digital core, the DAC, and a cascaded analog circuit. He uses Cadence Schematic Composer and Spectre in his research to create and simulate detailed analog circuit schematics, and to analyze analog and digital circuit noise during testing. The work won the N. N. Biswas Best Student Paper Prize at VLSI Design 2006, and is now being commercialized. He invented a jitter reduction circuit for clock trees in microprocessors, SERDES interfaces, and wireless radio receiver/transmitters. The invention will improve the performance of all phase-locked loops. This work appeared at NATW 2007. Starting work at Conexant Systems.
• Baozhen Yu: PhD Completed. Baozhen has invented a novel way to reduce deep submicron circuit leakage power drastically (by 90% or more) by switching off power supply voltages during each clock period. He uses Cadence Schematic Composer and Spectre in his research to validate whether his proposed method really reduces power consumption by performing detailed analog simulations (work appeared at ISLPED 2006 and ISCAS 2007). He will start work at nVidia.
• Raghuveer Ausoori: MS student. Raghuveer is developing a design-for-testability system for built-in self-test (BIST) to solve the problems of uninitialized flip-flops, high-impedance states, low fault coverage, and will cover stuck-at faults, delay faults, n-detect faults, and IDDQ faults. He uses Cadence Schematic Composer and Spectre in his research to validate whether his proposed method really reduces power consumption by performing detailed analog simulations.
• Shiva Gopalan: MS student. Shiva is creating a new wireless communications protocol for fault-tolerant hospital applications using CDMA in the FCC Wireless Medical Telemetry Spectrum band. He is implementing this system on WINLAB's ORBIT wireless test bench facility, and then will design the actual radio hardware. He does not use Cadence tools in his work.
• Wen Yueh: MS student. Wen is investigating novel flip-flop designs that are tolerant to two simultaneous single-event upsets. He uses Cadence tools in his work. This is a joint project with Alcatel-Lucent in Whippany, NJ.
• Srihitha Yerabaka: MS student. Srihitha is investigating improved power cutoff devices for low-power design. She uses Cadence tools in her work.
• Lakshmi Balasubramanian: MS student. Lakshmi is creating a fault-tolerant, low-power ARM microprocessor data path for use in fault-tolerant hospital applications. He is investigating the use of implications implemented in hardware to provide fault tolerance for finite state machine controllers. He uses Cadence tools in his work. He works at Dyalogic.
• Junwu Zhang: MS Completed. Junwu created a sequential circuit test-pattern generator that obtains much higher fault coverages, with much shorter pattern sequences, in far less CPU time, than other methods. He does not use Cadence tools in his work (published at ITC 2004).

• Current Research Funding

Cadence Value Added Items:

•  Cadence tool libraries for doing lambda-based designs for 0.35, 0.25, and 0.18 MOSIS technologies. These libraries and technology files are currently used by the ECE Dept. at City College of City University of New York. The libraries include a standard cell library for the 0.25 um TSMC process (Nov. 2004).
•  Technology files for MOSIS SCMOS processes (0.35, 0.25, and 0.18).
•  Technology files and standard cell libraries for a hypothetical 70 nm SCMOS process.
• MOSIS 0.18 um and 0.25um TSMC process Padframes.
• (pdf) A few Cadence tool usage tips in our academic manual for Cadence users.
• A verilog parser (based on the Berkeley verilog parser) for parsing verilog files produced by the Cadence system into our internal testing tool data base format.

Information is provided 'as is' without warranty of any kind. No statement is made and no attempt has been made to examine the information, either with respect to operability, origin, authorship, or otherwise. Please use this information at your own risk. We recommend using it on a copy of your data to be sure you understand what it does under your conditions. Keep your master intact until you are satisfied with the use of this information within your environment.

Cadence is a registered trademark of Cadence Design Systems, Inc., 2655 Seely Avenue, San Jose, CA 95134

Contact Prof. Bushnell by

• Snail-mail:

Prof. Michael Bushnell
CAIP Research Center
Rutgers University
96 Frelinghuysen Rd.
Piscataway, NJ 08854-8088

• Email:
  bushnell@caip.rutgers.edu
• Phone: (732)445-4854; Fax: (732)445-4775

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bushnell@caip.rutgers.edu; June 21, 2007