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Digital Systems Design, Fall 2007
14:332:437 Digital Systems Design, Fall 2007
Merry Christmas and a Happy New Year! The Final Exam, Practicum 1-4, Homework 1-10, and Exam 1-2 scores are now on sakai, and your grades are finalized. See Bushnell to question the grading of your Final exam. I will be India from 1/2/2008 through 1/9/2008, so see me on 12/31, or wait until I come back. Solutions to everything are on the table outside of CORE 624. The average on the Final was 53% and the course average on Exam 2 was 73%. Great job! Pick up your graded work from the table outside of Room CORE 624. Bushnell's Office Hours on Thursday are now adjusted to 3:00 p.m. to 4:00 p.m. and 8:00 p.m. to 9:00 p.m. Srihitha will hold office hours from now on in CORE 516. Current Field-Programmable Gate Arrays are using 70 nanometer chip technology, which is at the state of the chip making art!
Instructor:
Prof. Michael Bushnell (bushnell@caip.rutgers.edu)
Phone: (732) 445-4854
Lecture time: Mon., Wed. 3:20-4:40
Classroom: SEC-209
Course Laboratory: EE 103 and CORE 533 UNIX Work Station Rooms
Teaching Assistants
Srihitha Yerabaka, CORE 516 (srihitha@caip.rutgers.edu)
Phone: (732) 318-9768 Office hours: Mon., Fri. 1 - 2:30 p.m.
Administrative
Contact:
Lynn
Ruggiero (ruggiero@ece.rutgers.edu)
Phone: (732) 445-5241
Texts:
- Self-Checking and Fault-Tolerant Digital Design,
by Lala, Academic Press/HBJ, ISBN # 0-12-434370-8
- The Verilog Hardware Description Language, by Don Thomas and Philip Moorby, Kluwer, 2003, ISBN # 1-4020-7089-6
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Optional Text: Logic Design & Switching Theory, by Muroga, Krieger Publishing Co., ISBN # 1-57524-036-X
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Optional Text: Essentials of Electronic Testing for Digital, Memory, & Logic VLSI Circuits, by Bushnell and Agrawal, Springer, 2000, ISBN # 0-7923-7991-8
Synopsys Operating Instructions: postscript pdf
Course Syllabus: postscript pdf
Errors in Lala textbook: postscript pdf
Verilog Do's and Don'ts: postscript pdf
1997 Final Examination for study -- test and solution
1998 Final Examination for study -- test and solution
A Company Called IBM -- Used with permission from International Business Machines Corp.
"Error Detecting and Error Correcting Codes," by Richard W. Hamming, Bell System Technical Journal, 29(2): 16-29, 1950.
"A Signed Binary Multiplication Technique," by Andrew D. Booth, Quarterly Journal of Mechanical Applied Mathematics, 4: 236-240, 1951.
"A Logic for High-Speed Addition," by A. Weinberger and J. L. Smith, National Bureau of Standards Circular 591, pp 3-12, 1958.
"A Suggestion for a Fast Multiplier," by C. S. Wallace, IEEE Transactions on Electronic Computers, EC-13: 14-17, 1964.
Powerpoint Lecture Notes:
- Lecture 1 Fault Tolerance (powerpoint, 40 slides)
- Lecture 2 Fault Tolerance Examples (powerpoint, 33 slides)
- Lecture 3 Hardware Design Methodology and Advanced Logic Design (powerpoint, 23 slides)
- Lecture 4 Variable-Entered Karnaugh Maps and Mixed-Logic Design (powerpoint, 33 slides)
- Lecture 5 Verilog Tutorial (powerpoint, 24 slides)
- Lecture 6 Verilog Behavioral Modeling and Concurrency (powerpoint, 33 slides)
- Lecture 7 Verilog Hardware Description Language Basics (powerpoint, 19 slides)
- Lecture 8 Verilog and Finite State Machines (powerpoint, 23 slides)
- Lecture 9 Verilog Example (powerpoint, 31 slides) Verilog Code
- Lecture 10 Verilog Language Details (powerpoint, 29 slides)
- Lecture 11 Verilog Event-Driven Simulation (powerpoint, 41 slides)
- Lecture 12 Finite State Machine Design (powerpoint, 47 slides)
- Lecture 13 FSM Asynchronous Inputs, CLocks, and Hazards (powerpoint, 45 slides)
- Lecture 14 Turing Machines and State Machine Sequences (powerpoint, 18 slides)
- Lecture 15 System Controller Design (powerpoint, 18 slides)
- Lecture 16 FSM Synchronizers (powerpoint, 18 slides)
- Lecture 17 FSM Hardware Modification for Reliability (powerpoint, 20 slides)
- Lecture 18 Advanced Synchronizers (powerpoint, 18 slides)
- Lecture 19 Time Redundancy (powerpoint, 31 slides)
- Lecture 20 Information Redundancy (powerpoint, 40 slides)
- Lecture 21 Cyclic and Hamming Codes (powerpoint, 50 slides)
- Lecture 22 Computer Arithmetic (powerpoint, 29 slides)
- Lecture 23 Introduction to Testing (powerpoint, 32 slides)
- Lecture 24 Testing Methods (powerpoint, 39 slides)
- Lecture 25 Built-In Self-Testing (powerpoint, 26 slides)
- Lecture 26 IEEE Boundary Scan Standard and System Test (powerpoint, 32 slides)
- Lecture 27 Packaging (powerpoint, 5 slides)
Assignments:
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Note: Any questions about this
site, please email: bushnell@caip.rutgers.edu