//----------------------------------------------------
//TEST BENCHES (one test bench is commented out while running the other)
//For Part b

module test_bist(clk, reset, test, A, B, C, S1, S2, S3, F);

        output clk, reset, test, A, B, C;
        reg clk, reset, test, A, B, C;
        input S1, S2, S3, F;

        initial 
           begin
                $dumpvars;
                $dumpfile("bist3b.dump");
                $monitor("A = %b B = %b, C = %b F = %b", A, B, C, F);
                // Please print & submit the monitor output & virsim waveform
                
                        clk  = 0;
                        test = 0;
                                
                        #10 A = 0; B = 0; C = 0;
                        #10 A = 0; B = 0; C = 1;
                        #10 A = 0; B = 1; C = 0;
                        #10 A = 0; B = 1; C = 1;
                        #10 A = 1; B = 0; C = 0;
                        #10 A = 1; B = 0; C = 1;
                        #10 A = 1; B = 1; C = 0;
                        #10 A = 1; B = 1; C = 1;
                        #10 A = 0; B = 0; C = 0; //dummy case, to show ABC=111 on waveform
                        #10 $finish;          
           end
endmodule

//**********************************************
//For Parts c, d, e, g
/*
module test_bist(clk, reset, test, A, B, C, S1, S2, S3, F);

        output clk, reset, test, A, B, C;
        reg clk, reset, test, A, B, C;
        input S1, S2, S3, F;
     
        initial 
           begin
                $dumpvars;
                $dumpfile("bist3cdeg.dump");
                $monitor($time,,"S1 = %b S2 = %b, S3 = %b ", S1, S2, S3);
                // Please print & submit the monitor output & virsim waveform
                
                        clk  = 0;
                        A = 1'bz; B = 1'bz; C = 1'bz;
                        reset = 0;
                        test  = 1;
                        #10 clk = 1;
                        #10 clk = 0;    
                        reset = 1'bz;
                
                        #10 clk = 1;
                        #10 clk = 0;
                        #10 clk = 1;                        
                        #10 clk = 0;
                        #10 clk = 1;
                        #10 clk = 0;
                        #10 clk = 1;
                        #10 clk = 0;
                        #10 clk = 1;
                        #10 clk = 0;
                        #10 clk = 1;
                        #10 clk = 0;
                        #10 clk = 1;
                        #10 clk = 0;
                        #10 clk = 1;	
			#10 clk = 0; //dummy for waveform
			#10 $finish;            
           end
endmodule