// These values must be loaded into the Register file in the Register module
// for this test bench to work
  X[0] = 0;
  X[1] = 2;
  X[2] = 3;
  X[3] = 4;
  X[4] = 5;
  X[5] = 6;
  X[6] = 7;
  X[7] = 8;
  X[8] = 9;
  X[9] = 10;
  X[10] = 12;
  X[11] = 1;
  X[12] = 2;
  X[13] = 3;
  X[14] = 4;
  X[15] = 5;
  X[16] = 6;
  X[17] = 7;
  X[18] = 8;
  X[19] = 9;
  X[20] = 0;
  X[21] = 0;
  X[22] = 0;
  X[23] = 0;
  X[24] = 0;
  X[25] = 0;
  X[26] = 0;
  X[27] = 240;
  X[28] = -4;
  X[29] = 0;
  X[30] = 0;
  X[31] = 0;
// Actual test bench
        initial

                begin

                $dumpvars;
                $dumpfile("processor.dump");

                clk = 0;
                reset = 1;
                IR[31:24] = 8'h3A;
                IR[23:19] = 8;
                IR[18:14] = 9;
                IR[13:9]  = 15;
                IR[8:0]   = 0;


                #5      reset = 0;

                #15     IR[31:24] = 8'h3A;
			IR[23:19] = 8;
	                IR[18:14] = 2;
        	        IR[13:9]  = 9;
                	IR[8:0]   = 0;

		#20     IR[23:19] = 6;
                        IR[18:14] = 7;
                        IR[13:9]  = 7;
                        IR[8:0]   = 0;

                #20     IR[31:24] = 8'h21;
                        IR[23:19] = 8;
                        IR[18:14] = 1;
                        IR[13:9]  = 10;

                #20     IR[23:19] = 28;
                        IR[18:14] = 3;
                        IR[13:9]  = 11;


                #20     IR[31:24] = 8'h22;
                        IR[23:19] = 4;
                        IR[18:14] = 5;
                        IR[13:9]  = 12;

                #20     IR[23:19] = 27;
                        IR[18:14] = 4;
                        IR[13:9]  = 13;

		#20 	IR[31:24] = 8'h3A;
                        IR[23:19] = 18;
                        IR[18:14] = 18;
                        IR[13:9]  = 19;
                        
		#20     IR[31:24] = 8'h14;
                        IR[8:0]  = 9;


                #40 $finish;
                end



        always
                #5 clk = ~clk;