//***********************************
module testalu (a,b,s,z);
output reg [0:1]a, b, s;
input [0:1]z;
reg [0:4]i;

initial
begin
$dumpvars;
$dumpfile("HW2_alu.dump");
$monitor($time,,,"s=%b,a=%b,b=%b,z=%b",s,a,b,z);

#5 s=0;
for(i=0; i<16; i=i+1)
begin
{a,b} = i; #10;
end
#20 s=1;
for(i=0; i<16; i=i+1)
begin
{a,b} = i; #10;
end
#20 s=2;
for(i=0; i<16; i=i+1)
begin
{a,b} = i; #10;
end
#20 s=3;
for(i=0; i<16; i=i+1)
begin
{a,b} = i; #10;
end

#20 $finish;
end
endmodule