//*********************************************************

module testbench (clk,g,h,z1,z2,reset, present, next);
output clk, reset, g, h;
reg clk, reset, g, h;
input z1, z2;
input [0:2] present, next;

initial
  begin
    $dumpvars;
    $dumpfile("hw3p1.dump");

    $monitor ($time,,,"clk = %b reset = %b, g = %b h = %b, z1 = %b z2 = %b", 
              clk, reset, g, h, z1, z2);

    clk = 0;
    reset = 0;
    g = 0;
    h = 0;

#10 reset = 1; g = 1;
#10 h = 1;
#10 g = 0;
#10 g = 1; h = 0;
#30 g = 0;
#50 h = 1;
#30 g = 1; h = 0;
#20 g = 0; h = 1;
#40 h = 0;
#10 g = 0; h = 0;
#10 g = 0; h = 0;
#20 $finish;
end

always
#5 clk = ~clk;

endmodule