module testbench (clk, reset, SOFTWARE, TOP_GRADES, INDUSTRIAL_EXP, 
                  DIFFICULT_PERSON, MICRO_MANAGE, GREAT_TALKER, FOUR_OFFERS, 
                  FPGA, DSPCOM, VLSI, MEDICAL, SALARY, HOURS, DEFENSE_CO, 
                  INSTRUMENT_CO, DRUG_CO, MEDICAL_INSTR_CO, FINANCIAL_CO, 
                  CHIP_CO, SOFT_CO, COMMUNICATIONS_CO);

output clk, reset, SOFTWARE, TOP_GRADES, INDUSTRIAL_EXP, DIFFICULT_PERSON,
       MICRO_MANAGE, GREAT_TALKER, FOUR_OFFERS, FPGA, DSPCOM, VLSI, MEDICAL;
reg clk, reset, SOFTWARE, TOP_GRADES, INDUSTRIAL_EXP, DIFFICULT_PERSON, 
    MICRO_MANAGE, GREAT_TALKER, FOUR_OFFERS, FPGA, DSPCOM, VLSI, MEDICAL;

input [0:8] SALARY;
input [0:6] HOURS;
input DEFENSE_CO, INSTRUMENT_CO, DRUG_CO, MEDICAL_INSTR_CO, FINANCIAL_CO, 
      CHIP_CO, SOFT_CO, COMMUNICATIONS_CO;

initial 
  begin

    $dumpvars;
    $dumpfile("h3p2.dump");

    clk=0;
    reset = 0;
    SOFTWARE = 0; 
    TOP_GRADES = 0; 
    INDUSTRIAL_EXP = 0;
    DIFFICULT_PERSON = 0; 
    MICRO_MANAGE = 0; 
    GREAT_TALKER = 0; 
    FOUR_OFFERS = 0; 
    FPGA = 0; 
    DSPCOM = 0; 
    VLSI = 0; 
    MEDICAL = 0;

#10 reset =1;
#10 TOP_GRADES=1; INDUSTRIAL_EXP=1;
#10 INDUSTRIAL_EXP=0; DIFFICULT_PERSON=1; MICRO_MANAGE=1;
#10 MICRO_MANAGE=0; GREAT_TALKER =1;
#10 FOUR_OFFERS = 1;
#10 FOUR_OFFERS = 0; SOFTWARE=1;
#10 FPGA=1;
#10 SOFTWARE=0; FPGA = 0; VLSI=1;
#10 DSPCOM = 1;
#10 MEDICAL = 1;
#10 DSPCOM = 0;
#10 MEDICAL = 0; DSPCOM=1;
#10 VLSI=0;
#10 DSPCOM=0; MEDICAL=1;
#10 INDUSTRIAL_EXP = 1;
#10 FPGA = 1;
#10 MICRO_MANAGE=1; MEDICAL=0;
#20 $finish;

  end

always 
#5 clk = ~clk;

endmodule