// Put this code in your always block for the RegisterFile to initialize
// the register contents
    if (reset == 1)
      begin
        registers [0] = 0;
        registers [1] = 1;
        registers [2] = 2;
        registers [3] = 3;
        registers [4] = 4;
        registers [5] = 5;
        registers [6] = 6;
        registers [7] = 7;
        registers [8] = 8;
        registers [9] = 9;
        registers [10] = 10;
        registers [11] = 11;
        registers [12] = 12;
        registers [13] = 13;
        registers [14] = 14;
        registers [15] = 15;
      end

// Also include code in your RegisterFile to dump out the registers after
// each clock

// Testbench for Homework 5

module testbench (IR, clk, reset, ABUS, BBUS, CBUS, PCvalue);
output [0:31] IR;
reg [0:31] IR;
output clk, reset;
reg clk, reset;
input [0:31] ABUS;
input [0:31] BBUS;
input [0:63] CBUS;
input [0:31] PCvalue;

// Opcode definitions
parameter SUB = 8'h0A, MULT = 8'h1A, RRS = 8'h21, NANDOP = 8'h22,
          OROP = 8'h23, BRANCHIFZERO = 8'h14;

initial
  begin
    $dumpvars;
    $dumpfile ("hw5");
    clk = 0;
    reset = 1;
    IR = 0;
#10 reset = 0;
    // SUB instruction
    IR = {SUB, 5'd1, 5'd2, 5'd3};
#10
#10 // MULT instruction
    IR = {MULT, 5'd1, 5'd2, 5'd3};
#10
#10 // RRS instruction
    IR = {RRS, 5'd3, 5'd4, 5'd5};
#10
#10 // NAND instruction
    IR = {NANDOP, 5'd5, 5'd6, 5'd7};
#10
#10 // OR instruction
    IR = {OROP, 5'd7, 5'd8, 5'd9};
#10
#10 // BRANCHIFZERO instruction
    IR = {BRANCHIFZERO, 5'd0, 5'd0, 5'd0, 9'd7};
#10 $finish;
  end

always @(~clk)
#5  clk = ~ clk;

endmodule