14:332:438 Capstone Design -- Computer Systems, DSD Track, Spring 2008
  Your next meetings with Tapan will be on Friday, Feb. 1, 2008 in CORE 626 at the meeting times that you signed up for. Your 1/2 hour prerequisite exam will be on Friday, Feb. 8, 2008. Read DSD Lecture 1 powerpoint slides (below) for details on the project deadlines. Welcome to Capstone Design -- Computer Systems, DSD Track. You will learn, in this course, how to work on an Engineering Team to design a sizable digital system. Cheers!
Instructor:
Prof. Tapan J. Chakraborty (tchakraborty@alcatel-lucent.com) and Michael Bushnell (bushnell@caip.rutgers.edu)
Chakraborty's Office: CORE 613
Chakraborty's Address: Alcatel-Lucent Technologies, Room # 4C-332, 67 Whippany Road, Whippany, NJ 07981
Chakraborty's Phone: (973) 386-2443
Chakraborty's Office Hours: Friday, 12:30 p.m. - 2:00 p.m.
Bushnell's Office: CORE 624
Bushnell's Phone: (732) 445-4854
Bushnell's Office Hours: Tuesday and Thursday, 12:30-3:30 p.m.
Teaching Assistant: Srihitha Yerabaka
TA Office Hours:
Lecture time: Fri. 3:20-6:20
Classroom: Eng. B-120
Course Laboratory: EE 103 UNIX Work Station Room

Administrative Contact:
Lynn Ruggiero (ruggiero@ece.rutgers.edu)
Phone: (732) 445-5241

Texts:

• Self-Checking and Fault-Tolerant Digital Design, by Lala, Academic Press/HBJ, ISBN # 0-12-434370-8  
• The Verilog Hardware Description Language, by Don Thomas and Philip Moorby, Kluwer, 2003, ISBN # 1-4020-7089-6
• Optional Text: Logic Design & Switching Theory, by Muroga, Krieger Publishing Co., ISBN # 1-57524-036-X

Instructions for Using the Verilog Test Generator: postscript / pdf See Omar Khan or Mike Bushnell if you have problems.

Synopsys Operating Instructions: postscript pdf

FPGA Laboratory Instructions: pdf Xilinx PC tools manual (long and not printable): pdf

New include file to run Synopsys logic code on Xilinx tools: verilog

Course Syllabus: postscript pdf

Current Group Grades: postscript pdf

Sample Final Project Report: word

Sample Final Project Presentation: ppt

Sample Data Book Description: word

Errors in Lala textbook: postscript pdf

Verilog Do's and Don'ts: postscript pdf

A Company Called IBM -- Used with permission from International Business Machines Corp.

Lectures:

• Lecture 1 1/25/2008 Project Team Organization (powerpoint, 29 slides)
• Lectures 2-11 2/1/2008 - 4/4/2008 Weekly Individual Project Team Meetings
• Lecture 12 4/11/2008 Field Programmable Gate Arrays (FPGAs) (powerpoint, 55 slides)
• Lecture 13 4/18/2008 FPGA Downloading Laboratory (All Groups)
• Lecture 14 5/2/2008 Final Project Presentations

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Note: Any questions about this site, please email: bushnell@caip.rutgers.edu