`timescale 1ns / 1ps
///////////////////////////////////////////////////////////////////////////////
//
//        This confidential and proprietary software may be used only
//     as authorized by a licensing agreement from Synopsys Inc.
//     In the event of publication, the following notice is applicable:
//
//                    (C) COPYRIGHT 1994-1998 SYNOPSYS, INC.
//                              ALL RIGHTS RESERVED
//
//        The entire notice above must be reproduced on all authorized
//       copies.
//
// ABSTRACT: The GTECH library Verilog Simulation Model // ///////////////////////////////////////////////////////////////////////////////

//
// Verilog ATPG model for \**SEQGEN
//
module \**SEQGEN** (clear, preset, next_state, clocked_on, data_in, 
                    enable, Q, synch_clear,synch_preset,synch_toggle,
                    synch_enable);
input clear, preset, next_state,clocked_on, data_in, enable, synch_clear,
      synch_preset, synch_toggle,synch_enable;

output reg Q;

always@(posedge clocked_on or preset or clear)
  begin

      if(clear)
        begin
          Q <= 0;
        end
      else if(preset)
        begin
          Q <= 1;
        end
      else if(clocked_on)
        begin
          if(enable)
          begin
            if(synch_clear)
              Q <= 0;
            else if(synch_preset)
              Q <= 1;
            else if(synch_toggle)
              Q <= ~Q;
            else if(data_in)
              Q <= data_in;
            else
              Q <= next_state;
          end
        end

  end
endmodule

//
// Verilog Simulation model for GTECH_ADD_AB //

module GTECH_ADD_AB(A,B,S,COUT);
input	A,B;
output	S,COUT;
xor		U1(S,A,B);
and		U2(COUT,A,B);
endmodule
//
// Verilog Simulation model for GTECH_ADD_ABC //

module GTECH_ADD_ABC(A,B,C,S,COUT);
input	A,B,C;
output	S,COUT;
wire	AB,AC,BC;
xor		U1(S,A,B,C);
and			U2(AB,A,B);
and			U3(AC,A,C);
and			U4(BC,B,C);
or		U5(COUT,AB,AC,BC);
endmodule
//
// Verilog Simulation model for GTECH_AND2 //

module GTECH_AND2(A,B,Z);
input	A,B;
output	Z;
and		U(Z,A,B);
endmodule
//
// Verilog Simulation model for GTECH_AND3 //

module GTECH_AND3(A,B,C,Z);
input	A,B,C;
output	Z;
and		U(Z,A,B,C);
endmodule
//
// Verilog Simulation model for GTECH_AND4 //

module GTECH_AND4(A,B,C,D,Z);
input	A,B,C,D;
output	Z;
and		U(Z,A,B,C,D);
endmodule
//
// Verilog Simulation model for GTECH_AND5 //

module GTECH_AND5(A,B,C,D,E,Z);
input	A,B,C,D,E;
output	Z;
and		U(Z,A,B,C,D,E);
endmodule
//
// Verilog Simulation model for GTECH_AND8 //

module GTECH_AND8(A,B,C,D,E,F,G,H,Z);
input	A,B,C,D,E,F,G,H;
output	Z;
and		U(Z,A,B,C,D,E,F,G,H);
endmodule
//
// Verilog Simulation model for GTECH_AND_NOT //

module GTECH_AND_NOT(A,B,Z);
input	A,B;
output	Z;
wire	BN;
not			U1(BN,B);
and		U2(Z,A,BN);
endmodule
//
// Verilog Simulation model for GTECH_AO21 //

module GTECH_AO21(A,B,C,Z);
input	A,B,C;
output	Z;
wire	AB;
and			U1(AB,A,B);
or		U2(Z,AB,C);
endmodule
//
// Verilog Simulation model for GTECH_AO22 //

module GTECH_AO22(A,B,C,D,Z);
input	A,B,C,D;
output	Z;
wire	AB,CD;
and			U1(AB,A,B);
and			U2(CD,C,D);
or		U3(Z,AB,CD);
endmodule
//
// Verilog Simulation model for GTECH_AOI21 //

module GTECH_AOI21(A,B,C,Z);
input	A,B,C;
output	Z;
wire	AB;
and			U1(AB,A,B);
nor		U2(Z,AB,C);
endmodule
//
// Verilog Simulation model for GTECH_AOI22 //

module GTECH_AOI22(A,B,C,D,Z);
input	A,B,C,D;
output	Z;
wire	AB,CD;
and			U1(AB,A,B);
and			U2(CD,C,D);
nor		U3(Z,AB,CD);
endmodule
//
// Verilog Simulation model for GTECH_AOI222 //

module GTECH_AOI222(A,B,C,D,E,F,Z);
input	A,B,C,D,E,F;
output	Z;
wire	AB,CD,EF;
and			U1(AB,A,B);
and			U2(CD,C,D);
and			U3(EF,E,F);
nor		U4(Z,AB,CD,EF);
endmodule
//
// Verilog Simulation model for GTECH_AOI2N2 //

module GTECH_AOI2N2(A,B,C,D,Z);
input	A,B,C,D;
output	Z;
wire	AB,CD;
and			U1(AB,A,B);
nor			U2(CD,C,D);
nor		U3(Z,AB,CD);
endmodule
//
// Verilog Simulation model for GTECH_BUF //

module GTECH_BUF(A,Z);
input	A;
output	Z;
buf		U(Z,A);
endmodule
//
// Verilog User Module definition for GTECH_UDP_FD1 //

module GTECH_UDP_FD1 ( Q, D, CP );
input  D, CP;
output Q;
    \**SEQGEN**  Q_reg ( .clear(1'b0), .preset(1'b0), .next_state(D), 
        .clocked_on(CP), .data_in(1'b0), .enable(1'b0), .Q(Q), .synch_clear(
        1'b0), .synch_preset(1'b0), .synch_toggle(1'b0), .synch_enable(1'b1)
         );
endmodule

//
// Verilog Simulation model for GTECH_FD1 //

module GTECH_FD1(D,CP,Q,QN);
input	D,CP;
output	Q,QN;

        GTECH_UDP_FD1 A (Q_int, D, CP);
        buf  (Q, Q_int);
        not  (QN, Q_int);

endmodule
//
// Verilog Simulation model for GTECH_FD14 //

module GTECH_FD14(D0, D1, D2, D3, CP,
		Q0, Q1, Q2, Q3,
		QN0, QN1, QN2, QN3);
input		D0;
input		D1;
input		D2;
input		D3;
input		CP;
output		Q0,QN0;
output		Q1,QN1;
output		Q2,QN2;
output		Q3,QN3;

        GTECH_UDP_FD1 A (Q0_int, D0, CP);
        GTECH_UDP_FD1 B (Q1_int, D1, CP);
        GTECH_UDP_FD1 C (Q2_int, D2, CP);
        GTECH_UDP_FD1 D (Q3_int, D3, CP);
        buf  (Q0, Q0_int); 
        buf  (Q1, Q1_int); 
        buf  (Q2, Q2_int); 
        buf  (Q3, Q3_int); 
        not  (QN0, Q0_int);  
        not  (QN1, Q1_int);
        not  (QN2, Q2_int);
        not  (QN3, Q3_int);
endmodule
//
// Verilog Simulation model for GTECH_FD18 //

module GTECH_FD18(D0, D1, D2, D3, D4, D5, D6, D7, CP,
		Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7,
		QN0, QN1, QN2, QN3, QN4, QN5, QN6, QN7);
input		D0;
input		D1;
input		D2;
input		D3;
input		D4;
input		D5;
input		D6;
input		D7;
input		CP;
output		Q0,QN0;
output		Q1,QN1;
output		Q2,QN2;
output		Q3,QN3;
output		Q4,QN4;
output		Q5,QN5;
output		Q6,QN6;
output		Q7,QN7;

        GTECH_UDP_FD1 A  (Q0_int, D0, CP);
        GTECH_UDP_FD1 B (Q1_int, D1, CP);
        GTECH_UDP_FD1 C (Q2_int, D2, CP);
        GTECH_UDP_FD1 D (Q3_int, D3, CP);
        GTECH_UDP_FD1 E (Q4_int, D4, CP);
        GTECH_UDP_FD1 F (Q5_int, D5, CP);
        GTECH_UDP_FD1 G (Q6_int, D6, CP);
        GTECH_UDP_FD1 H (Q7_int, D7, CP);
        buf  (Q0, Q0_int);  
        buf  (Q1, Q1_int);
        buf  (Q2, Q2_int);
        buf  (Q3, Q3_int);
        buf  (Q4, Q4_int);  
        buf  (Q5, Q5_int);
        buf  (Q6, Q6_int);
        buf  (Q7, Q7_int);
        not  (QN0, Q0_int);   
        not  (QN1, Q1_int);
        not  (QN2, Q2_int); 
        not  (QN3, Q3_int); 
        not  (QN4, Q4_int);   
        not  (QN5, Q5_int);
        not  (QN6, Q6_int); 
        not  (QN7, Q7_int);
endmodule
module GTECH_UDP_MUX2 (Z, A, B, S);
    output Z;
    input A, B, S;
wire Sbar, z1, z2;

    // FUNCTION: 2:1 MUX

not i4 (Sbar, S);
nand i1 (z1, Sbar, A);
nand i2 (z2, S, B);
nand i3 (Z, z1, z2);

endmodule

//
// Verilog Simulation model for GTECH_FD1S //

module GTECH_FD1S(D,TI,TE,CP,Q,QN);
input	D,TI,TE,CP;
output	Q,QN;

        GTECH_UDP_MUX2 A (DT, D, TI, TE);
        GTECH_UDP_FD1 B (Q_int, DT, CP);
        buf  (Q, Q_int);
        not  (QN, Q_int);
endmodule
//
// Verilog User Module definition for GTECH_UDP_FD2 //

module GTECH_UDP_FD2 ( Q, D, CP, CD );
input  D, CP, CD;
output Q;
    wire n62;
    GTECH_NOT U16 ( .A(CD), .Z(n62) );
    \**SEQGEN**  Q_reg ( .clear(n62), .preset(1'b0), .next_state(D), 
        .clocked_on(CP), .data_in(1'b0), .enable(1'b0), .Q(Q), 
        .synch_clear(1'b0), .synch_preset(1'b0), .synch_toggle(1'b0), 
        .synch_enable(1'b1) );
endmodule

//
// Verilog Simulation model for GTECH_FD2 //

module GTECH_FD2(D,CP,CD,Q,QN);
input	D,CP,CD;
output	Q,QN;

        GTECH_UDP_FD2 A (Q_int, D, CP, CD); 
        buf  (Q, Q_int); 
        not  (QN, Q_int); 

endmodule
//
// Verilog Simulation model for GTECH_FD24 //

module GTECH_FD24(D0, D1, D2, D3, CP, CD,
		Q0, Q1, Q2, Q3,
		QN0, QN1, QN2, QN3);
input		D0;
input		D1;
input		D2;
input		D3;
input		CP;
input		CD;
output		Q0,QN0;
output		Q1,QN1;
output		Q2,QN2;
output		Q3,QN3;

        GTECH_UDP_FD2 A (Q0_int, D0, CP, CD);
        GTECH_UDP_FD2 B (Q1_int, D1, CP, CD);
        GTECH_UDP_FD2 C (Q2_int, D2, CP, CD);
        GTECH_UDP_FD2 D (Q3_int, D3, CP, CD);
        buf  (Q0, Q0_int);
        buf  (Q1, Q1_int);
        buf  (Q2, Q2_int);
        buf  (Q3, Q3_int);
        not  (QN0, Q0_int);
        not  (QN1, Q1_int);
        not  (QN2, Q2_int);
        not  (QN3, Q3_int);
endmodule
//
// Verilog Simulation model for GTECH_FD28 //

module GTECH_FD28(D0, D1, D2, D3, D4, D5, D6, D7, CP, CD,
		Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7,
		QN0, QN1, QN2, QN3, QN4, QN5, QN6, QN7);
input		D0;
input		D1;
input		D2;
input		D3;
input		D4;
input		D5;
input		D6;
input		D7;
input		CP;
input		CD;
output		Q0,QN0;
output		Q1,QN1;
output		Q2,QN2;
output		Q3,QN3;
output		Q4,QN4;
output		Q5,QN5;
output		Q6,QN6;
output		Q7,QN7;


        GTECH_UDP_FD2 A (Q0_int, D0, CP, CD);
        GTECH_UDP_FD2 B (Q1_int, D1, CP, CD);
        GTECH_UDP_FD2 C (Q2_int, D2, CP, CD);
        GTECH_UDP_FD2 D (Q3_int, D3, CP, CD);
        GTECH_UDP_FD2 E (Q4_int, D4, CP, CD);
        GTECH_UDP_FD2 F (Q5_int, D5, CP, CD);
        GTECH_UDP_FD2 G (Q6_int, D6, CP, CD);
        GTECH_UDP_FD2 H (Q7_int, D7, CP, CD);
        buf  (Q0, Q0_int);
        buf  (Q1, Q1_int);
        buf  (Q2, Q2_int);
        buf  (Q3, Q3_int);
        buf  (Q4, Q4_int);
        buf  (Q5, Q5_int);
        buf  (Q6, Q6_int);
        buf  (Q7, Q7_int);
        not  (QN0, Q0_int);
        not  (QN1, Q1_int);
        not  (QN2, Q2_int);
        not  (QN3, Q3_int);
        not  (QN4, Q4_int);
        not  (QN5, Q5_int);
        not  (QN6, Q6_int);
        not  (QN7, Q7_int);

endmodule
//
// Verilog Simulation model for GTECH_FD2S //

module GTECH_FD2S(D,TI,TE,CP,CD,Q,QN);
input	D,TI,TE,CP,CD;
output	Q,QN;

        GTECH_UDP_MUX2 A (DT, D, TI, TE);
        GTECH_UDP_FD2 B (Q_int, DT, CP, CD);
        buf  (Q, Q_int);
        not  (QN, Q_int);


endmodule
//
// Verilog User Module definition for GTECH_UDP_FD3 //

module GTECH_UDP_FD3 ( Q, D, CP, CD, SD ); input  D, CP, CD, SD; output Q;
    wire n91, n95;
    GTECH_NOT U27 ( .A(CD), .Z(n91) );
    GTECH_NOT U31 ( .A(SD), .Z(n95) );
    \**SEQGEN**  Q_reg ( .clear(n91), .preset(n95), .next_state(D), 
        .clocked_on(CP), .data_in(1'b0 ), .enable(1'b0), .Q(Q), 
        .synch_clear(1'b0), .synch_preset(1'b0), .synch_toggle(1'b0), 
        .synch_enable(1'b1) );
endmodule

//
// Verilog Simulation model for GTECH_FD3 //

module GTECH_FD3(D,CP,CD,SD,Q,QN);
input	D,CP,CD,SD;
output	Q,QN;
wire Q_int_int;

        GTECH_UDP_FD3 A (Q_int, D, CP, CD, SD); 
        buf  (Q, Q_int); 
        assign Q_int_int = ((SD === 1'b0) & (CD === 1'b0))?1'b1: Q_int;
        not  (QN, Q_int_int);
endmodule
//
// Verilog Simulation model for GTECH_FD34 //

module GTECH_FD34(D0, D1, D2, D3, CP, CD, SD,
		Q0, Q1, Q2, Q3,
		QN0, QN1, QN2, QN3);
input		D0;
input		D1;
input		D2;
input		D3;
input		CP,CD,SD;
output		Q0,QN0;
output		Q1,QN1;
output		Q2,QN2;
output		Q3,QN3;

        GTECH_UDP_FD3 FD34_00 (Q0_int, D0, CP, CD, SD);
        GTECH_UDP_FD3 FD34_01 (Q1_int, D1, CP, CD, SD);
        GTECH_UDP_FD3 FD34_02 (Q2_int, D2, CP, CD, SD);
        GTECH_UDP_FD3 FD34_03 (Q3_int, D3, CP, CD, SD);
        buf  (Q0, Q0_int); 
        buf  (Q1, Q1_int); 
        buf  (Q2, Q2_int); 
        buf  (Q3, Q3_int); 
        not  (QN0, Q0_int);  
        not  (QN1, Q1_int);
        not  (QN2, Q2_int);
        not  (QN3, Q3_int);

endmodule
//
// Verilog Simulation model for GTECH_FD38 //

module GTECH_FD38(D0, D1, D2, D3, D4, D5, D6, D7, CP, CD, SD,
		Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7,
		QN0, QN1, QN2, QN3, QN4, QN5, QN6, QN7);
input		D0;
input		D1;
input		D2;
input		D3;
input		D4;
input		D5;
input		D6;
input		D7;
input		CP,CD,SD;
output		Q0,QN0;
output		Q1,QN1;
output		Q2,QN2;
output		Q3,QN3;
output		Q4,QN4;
output		Q5,QN5;
output		Q6,QN6;
output		Q7,QN7;

        GTECH_UDP_FD3 FD38_00 (Q0_int, D0, CP, CD, SD);
        GTECH_UDP_FD3 FD38_01 (Q1_int, D1, CP, CD, SD);
        GTECH_UDP_FD3 FD38_02 (Q2_int, D2, CP, CD, SD);
        GTECH_UDP_FD3 FD38_03 (Q3_int, D3, CP, CD, SD);
        GTECH_UDP_FD3 FD38_04 (Q4_int, D4, CP, CD, SD);
        GTECH_UDP_FD3 FD38_05 (Q5_int, D5, CP, CD, SD);
        GTECH_UDP_FD3 FD38_06 (Q6_int, D6, CP, CD, SD);
        GTECH_UDP_FD3 FD38_07 (Q7_int, D7, CP, CD, SD);
        buf  (Q0, Q0_int); 
        buf  (Q1, Q1_int); 
        buf  (Q2, Q2_int); 
        buf  (Q3, Q3_int); 
        buf  (Q4, Q4_int); 
        buf  (Q5, Q5_int); 
        buf  (Q6, Q6_int); 
        buf  (Q7, Q7_int); 
        not  (QN0, Q0_int);  
        not  (QN1, Q1_int);
        not  (QN2, Q2_int);
        not  (QN3, Q3_int);
        not  (QN4, Q4_int);  
        not  (QN5, Q5_int);
        not  (QN6, Q6_int);
        not  (QN7, Q7_int);

endmodule
//
// Verilog Simulation model for GTECH_FD3S //

module GTECH_FD3S(D,TI,TE,CP,CD,SD,Q,QN);
input	D,TI,TE,CP,CD,SD;
output	Q,QN;
wire Q_int_int;

        GTECH_UDP_MUX2 A (DT, D, TI, TE);
        GTECH_UDP_FD3 B (Q_int, DT, CP, CD, SD);
        buf  (Q, Q_int);
        assign Q_int_int = ((SD === 1'b0) & (CD === 1'b0))?1'b1: Q_int;
        not  (QN, Q_int_int);

endmodule
//
// Verilog User Module definition for GTECH_UDP_FD4 //

module GTECH_UDP_FD4 ( Q, D, CP, SD );
input  D, CP, SD;
output Q;
    wire n62;
    GTECH_NOT U16 ( .A(SD), .Z(n62) );
    \**SEQGEN**  Q_reg ( .clear(1'b0), .preset(n62), .next_state(D), 
        .clocked_on(CP), .data_in(1'b0), .enable(1'b0), .Q(Q), 
        .synch_clear(1'b0), .synch_preset(1'b0), .synch_toggle(1'b0), 
        .synch_enable(1'b1) );
endmodule

//
// Verilog Simulation model for GTECH_FD4 //

module GTECH_FD4(D,CP,SD,Q,QN);
input	D,CP,SD;
output	Q,QN;

        GTECH_UDP_FD4 A (Q_int, D, CP, SD); 
        buf  (Q, Q_int);   
        not  (QN, Q_int); 

endmodule
//
// Verilog Simulation model for GTECH_FD44 //

module GTECH_FD44(D0, D1, D2, D3, CP, SD,
		Q0, Q1, Q2, Q3,
		QN0, QN1, QN2, QN3);
input		D0;
input		D1;
input		D2;
input		D3;
input		CP;
input		SD;
output		Q0,QN0;
output		Q1,QN1;
output		Q2,QN2;
output		Q3,QN3;

        GTECH_UDP_FD4 A (Q0_int, D0, CP, SD);
        GTECH_UDP_FD4 B (Q1_int, D1, CP, SD);
        GTECH_UDP_FD4 C (Q2_int, D2, CP, SD);
        GTECH_UDP_FD4 D (Q3_int, D3, CP, SD);
        buf  (Q0, Q0_int);
        buf  (Q1, Q1_int);
        buf  (Q2, Q2_int);
        buf  (Q3, Q3_int);
        not  (QN0, Q0_int);
        not  (QN1, Q1_int);
        not  (QN2, Q2_int);
        not  (QN3, Q3_int);

endmodule
//
// Verilog Simulation model for GTECH_FD48 //

module GTECH_FD48(D0, D1, D2, D3, D4, D5, D6, D7, CP, SD,
		Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7,
		QN0, QN1, QN2, QN3, QN4, QN5, QN6, QN7);
input		D0;
input		D1;
input		D2;
input		D3;
input		D4;
input		D5;
input		D6;
input		D7;
input		CP;
input		SD;
output		Q0,QN0;
output		Q1,QN1;
output		Q2,QN2;
output		Q3,QN3;
output		Q4,QN4;
output		Q5,QN5;
output		Q6,QN6;
output		Q7,QN7;

        GTECH_UDP_FD4 A  (Q0_int, D0, CP, SD);
        GTECH_UDP_FD4 B (Q1_int, D1, CP, SD);
        GTECH_UDP_FD4 C (Q2_int, D2, CP, SD);
        GTECH_UDP_FD4 D (Q3_int, D3, CP, SD);
        GTECH_UDP_FD4 E (Q4_int, D4, CP, SD);
        GTECH_UDP_FD4 F (Q5_int, D5, CP, SD);
        GTECH_UDP_FD4 G (Q6_int, D6, CP, SD);
        GTECH_UDP_FD4 H (Q7_int, D7, CP, SD);
        buf  (Q0, Q0_int);
        buf  (Q1, Q1_int);
        buf  (Q2, Q2_int);
        buf  (Q3, Q3_int);
        buf  (Q4, Q4_int);
        buf  (Q5, Q5_int);
        buf  (Q6, Q6_int);
        buf  (Q7, Q7_int);
        not  (QN0, Q0_int);
        not  (QN1, Q1_int);
        not  (QN2, Q2_int);
        not  (QN3, Q3_int);
        not  (QN4, Q4_int);
        not  (QN5, Q5_int);
        not  (QN6, Q6_int);
        not  (QN7, Q7_int);

endmodule
//
// Verilog Simulation model for GTECH_FD4S //

module GTECH_FD4S(D,TI,TE,CP,SD,Q,QN);
input	D,TI,TE,CP,SD;
output	Q,QN;

        GTECH_UDP_MUX2 A (DT, D, TI, TE);
        GTECH_UDP_FD4 B (Q_int, DT, CP, SD);
        buf  (Q, Q_int);
        not  (QN, Q_int);

endmodule
//
// Verilog User Module definition for GTECH_UDP_FJK1 //

module GTECH_UDP_FJK1 ( Q, J, K, CP );
input  J, K, CP;
output Q;
    wire D, Qbar, or1_op, Kbar;
    \**SEQGEN**  Q_reg ( .clear(1'b0), .preset(1'b0), .next_state(D), 
        .clocked_on(CP), .data_in(1'b0), .enable(1'b0), .Q(Q), .synch_clear(
        1'b0), .synch_preset(1'b0), .synch_toggle(1'b0), .synch_enable(or1_op)
         );
    GTECH_OR2 u1 ( .A(J), .B(K), .Z(or1_op) );
    GTECH_MUX4 u2 ( .D0(Q), .D1(J), .D2(Kbar), .D3(Qbar), .A(J), .B(K), .Z(D)
         );
    GTECH_NOT u3 ( .A(Q), .Z(Qbar) );
    GTECH_NOT u4 ( .A(K), .Z(Kbar) );
endmodule
//
// Verilog Simulation model for GTECH_FJK1 //

module GTECH_FJK1(J,K,CP,Q,QN);
input	J,K,CP;
output	Q,QN;
   
        GTECH_UDP_FJK1 A (Q_int, J, K, CP);
        buf  (Q, Q_int);
        not  (QN, Q_int);

endmodule
//
// Verilog Simulation model for GTECH_FJK1S //

module GTECH_FJK1S(J,K,TI,TE,CP,Q,QN);
input	J,K,TI,TE,CP;
output	Q,QN;

        not (TIB, TI);
        GTECH_UDP_MUX2 A (J_int, J, TI, TE);
        GTECH_UDP_MUX2 B (K_int, K, TIB, TE);
        GTECH_UDP_FJK1 C (Q_int, J_int, K_int, CP);
        buf  (Q, Q_int);
        not  (QN, Q_int);

endmodule
//
// Verilog User Module definition for GTECH_UDP_FJK2 //

module GTECH_UDP_FJK2 ( Q, J, K, CP, CD ); input  J, K, CP, CD; output Q;
    wire CDBar, D, Qbar, Kbar;
    GTECH_NOT u5 ( .A(CD), .Z(CDBar) );
    \**SEQGEN**  Q_reg ( .clear(CDBar), .preset(1'b0), .next_state(D), 
        .clocked_on(CP), .data_in(1'b0), .enable(1'b0), .Q(Q), .synch_clear(
        1'b0), .synch_preset(1'b0), .synch_toggle(1'b0), .synch_enable(1'b1)
         );
    GTECH_MUX4 u2 ( .D0(Q), .D1(J), .D2(Kbar), .D3(Qbar), .A(J), .B(K), .Z(D)
         );
    GTECH_NOT u3 ( .A(Q), .Z(Qbar) );
    GTECH_NOT u4 ( .A(K), .Z(Kbar) );
endmodule
//
// Verilog Simulation model for GTECH_FJK2 //

module GTECH_FJK2(J,K,CP,CD,Q,QN);
input	J,K,CP,CD;
output	Q,QN;

        GTECH_UDP_FJK2 A (Q_int, J, K, CP, CD); 
        buf  (Q, Q_int); 
        not  (QN, Q_int); 

endmodule
//
// Verilog Simulation model for GTECH_FJK2S //

module GTECH_FJK2S(J,K,TI,TE,CP,CD,Q,QN);
input	J,K,TI,TE,CP,CD;
output	Q,QN;

        not (TIB, TI); 
        GTECH_UDP_MUX2 A (J_int, J, TI, TE);
        GTECH_UDP_MUX2 B (K_int, K, TIB, TE);
        GTECH_UDP_FJK2 C (Q_int, J_int, K_int, CP, CD); 
        buf  (Q, Q_int); 
        not  (QN, Q_int); 

endmodule
//
// Verilog User Module definition for GTECH_UDP_FJK3 //

module GTECH_UDP_FJK3 ( Q, J, K, CP, CD, SD ); input  J, K, CP, CD, SD; output Q;
    wire CDBar, D, Qbar, SDBar, Kbar;
    GTECH_NOT u5 ( .A(CD), .Z(CDBar) );
    GTECH_NOT u6 ( .A(SD), .Z(SDBar) );
    \**SEQGEN**  Q_reg ( .clear(CDBar), .preset(SDBar), .next_state(D), 
        .clocked_on(CP), .data_in(1'b0), .enable(1'b0), .Q(Q), .synch_clear(
        1'b0), .synch_preset(1'b0), .synch_toggle(1'b0), .synch_enable(1'b1)
         );
    GTECH_MUX4 u2 ( .D0(Q), .D1(J), .D2(Kbar), .D3(Qbar), .A(J), .B(K), .Z(D)
         );
    GTECH_NOT u3 ( .A(Q), .Z(Qbar) );
    GTECH_NOT u4 ( .A(K), .Z(Kbar) );
endmodule
//
// Verilog Simulation model for GTECH_FJK3 //

module GTECH_FJK3(J,K,CP,CD,SD,Q,QN);
input	J,K,CP,CD,SD;
output	Q,QN;
wire Q_int_int;

        GTECH_UDP_FJK3 A (Q_int, J, K, CP, CD, SD);  
        buf  (Q, Q_int);  
        assign Q_int_int = ((SD === 1'b0) & (CD === 1'b0))?1'b1: Q_int;
        not  (QN, Q_int_int); 

endmodule
//
// Verilog Simulation model for GTECH_FJK3S //

module GTECH_FJK3S(J,K,TI,TE,CP,CD,SD,Q,QN);
input	J,K,TI,TE,CP,CD,SD;
output	Q,QN;
wire Q_int_int;

        not (TIB, TI); 
        GTECH_UDP_MUX2 A (J_int, J, TI, TE);
        GTECH_UDP_MUX2 B (K_int, K, TIB, TE);
        GTECH_UDP_FJK3 C (Q_int, J_int, K_int, CP, CD, SD);
        buf  (Q, Q_int);   
        assign Q_int_int = ((SD === 1'b0) & (CD === 1'b0))?1'b1: Q_int;
        not  (QN, Q_int_int); 

endmodule
//
// Verilog User Module definition for GTECH_UDP_FJK4 //

module GTECH_UDP_FJK4 ( Q, J, K, CP, SD ); input  J, K, CP, SD; output Q;
    wire SDBar, D, Qbar, or1_op, Kbar;
    GTECH_NOT u5 ( .A(SD), .Z(SDBar) );
    \**SEQGEN**  Q_reg ( .clear(1'b0), .preset(SDBar), .next_state(D), 
        .clocked_on(CP), .data_in(1'b0), .enable(1'b0), .Q(Q), .synch_clear(
        1'b0), .synch_preset(1'b0), .synch_toggle(1'b0), .synch_enable(or1_op)
         );
    GTECH_OR2 u1 ( .A(J), .B(K), .Z(or1_op) );
    GTECH_MUX4 u2 ( .D0(Q), .D1(J), .D2(Kbar), .D3(Qbar), .A(J), .B(K), .Z(D)
         );
    GTECH_NOT u3 ( .A(Q), .Z(Qbar) );
    GTECH_NOT u4 ( .A(K), .Z(Kbar) );
endmodule
//
// Verilog Simulation model for GTECH_FJK4 //

module GTECH_FJK4(J,K,CP,SD,Q,QN);
input	J,K,CP,SD;
output	Q,QN;

        GTECH_UDP_FJK4 A (Q_int, J, K, CP, SD);
        buf  (Q, Q_int);      
        not  (QN, Q_int);   

endmodule
//
// Verilog Simulation model for GTECH_FJK4S //

module GTECH_FJK4S(J,K,TI,TE,CP,SD,Q,QN);
input	J,K,TI,TE,CP,SD;
output	Q,QN;

        not (TIB, TI); 
        GTECH_UDP_MUX2 A (J_int, J, TI, TE);
        GTECH_UDP_MUX2 B (K_int, K, TIB, TE);
        GTECH_UDP_FJK4 C (Q_int, J_int, K_int, CP, SD);
        buf  (Q, Q_int);      
        not  (QN, Q_int);   
endmodule
//
// Verilog Simulation model for GTECH_INBUF //

module GTECH_INBUF(PAD_IN,DATA_IN);
output	DATA_IN;
input	PAD_IN;
assign   DATA_IN = PAD_IN & 1'b1;
endmodule
//
// Verilog Simulation model for GTECH_INOUTBUF //

module GTECH_INOUTBUF(DATA_OUT,OE,PAD_INOUT,DATA_IN);
input	DATA_OUT,OE;
output	DATA_IN;
inout	PAD_INOUT;
assign	 PAD_INOUT = OE? (DATA_OUT & 1'b1) : 1'bz;
assign   DATA_IN = PAD_INOUT & 1'b1;
endmodule
//
// Verilog User Module definition for GTECH_UDP_LD1 //
module GTECH_UDP_LD1_Q(Q,D,G);
output reg Q;
input D,G;

always@(D)
begin
  if(G)
    Q <= D;
end

endmodule

//
// Verilog Simulation model for GTECH_LD1 //

module GTECH_LD1(D,G,Q,QN);
input	D,G;
output	Q,QN;

        GTECH_UDP_LD1_Q A (Q_int, D, G); 
        buf  (Q, Q_int);       
        not  (QN, Q_int);    

endmodule
//
// Verilog User Module definition for GTECH_UDP_LD2 //
module GTECH_UDP_LD2_Q(Q,D,G);
output reg Q;
input D,G;

always@(D)
begin
  if(~G)
    Q <= D;
end

endmodule

//
// Verilog Simulation model for GTECH_LD2 //

module GTECH_LD2(D,GN,Q,QN);
input	D,GN;
output	Q,QN;

        GTECH_UDP_LD2_Q A (Q_int, D, GN);  
        buf  (Q, Q_int);        
        not  (QN, Q_int);     
endmodule
//
// Verilog Simulation model for GTECH_LD2_1 //

module GTECH_LD2_1(D,GN,Q);
input   D,GN;
output  Q;
 
        GTECH_UDP_LD2_Q A (Q_int, D, GN);
        buf  (Q, Q_int);
endmodule
//
// Verilog User Module definition for GTECH_UDP_LD3 //
module GTECH_UDP_LD3_Q(Q,D,G,CD);
output reg Q;  //output of latch
input D;       //input to latch
input G;       //enable the latch -- active high
input CD;      //async clear -- active low

always@(D or CD)
begin
  if(~CD)
    Q <= 0;
  else if (G && CD)
    Q<=D;
    
end

endmodule

//
// Verilog Simulation model for GTECH_LD3 //

module GTECH_LD3(D,G,CD,Q,QN);
input	D,G,CD;
output	Q,QN;

        GTECH_UDP_LD3_Q A (Q_int, D, G, CD);   
        buf  (Q, Q_int);         
        not  (QN, Q_int);      

endmodule
//
// Verilog User Module definition for GTECH_UDP_LD4 //
module GTECH_UDP_LD4_Q(Q,D,G,CD);
output reg Q;  //output of latch
input D;       //input to latch
input G;       //enable the latch -- active high
input CD;      //async clear -- active low

always@(D or CD)
begin
  if(~CD)
    Q <= 0;
  else if (~G && CD)
    Q<=D;
    
end

endmodule

//
// Verilog Simulation model for GTECH_LD4 //

module GTECH_LD4(D,GN,CD,Q,QN);
input	D,GN,CD;
output	Q,QN;

        GTECH_UDP_LD4_Q A (Q_int, D, GN, CD);    
        buf  (Q, Q_int);          
        not  (QN, Q_int);      

endmodule
//
// Verilog Simulation model for GTECH_LD4_1 //

module GTECH_LD4_1(D,GN,CD,Q);
input   D,GN,CD;
output  Q;
 
        GTECH_UDP_LD4_Q A (Q_int, D, GN, CD);
        buf  (Q, Q_int);
endmodule
//
// Verilog User Module definition for GTECH_UDP_LSR0 //

module GTECH_UDP_LSR0_Q(Q,S,R);
  output reg Q;
  input S,R;

  always@(S or R)
    begin
      case({S,R})
        2'bx0: Q<=0;
        2'b01: Q<=1;
        2'b10: Q<=0;
        2'b11: Q<=Q;
        default: Q<=Q;
      endcase
    end
endmodule
//
// Verilog Simulation model for GTECH_LSR0 //

module GTECH_LSR0(S,R,Q,QN);
input	S,R;
output	Q,QN;
wire Q_int_int;

        GTECH_UDP_LSR0_Q A (Q_int, S, R);    
        buf  (Q, Q_int);           
        assign Q_int_int = ((S === 1'b0) & (R === 1'b0))?1'b1: Q_int;
        not  (QN, Q_int_int);

endmodule
//
// Verilog Simulation model for GTECH_MAJ23 //

module GTECH_MAJ23(A,B,C,Z);
input	A,B,C;
output	Z;
wire	AB,AC,BC;
and			U1(AB,A,B);
and			U2(AC,A,C);
and			U3(BC,B,C);
or		U4(Z,AB,AC,BC);
endmodule
//
// Verilog Simulation model for GTECH_MUX2 //

module GTECH_MUX2(A,B,S,Z);
input	A,B,S;
output	Z;
       
        GTECH_UDP_MUX2 U1 (Z_int, A, B, S);
        buf  (Z, Z_int);
endmodule
//
// Verilog User Module definition for GTECH_UDP_MUX4 //

module GTECH_UDP_MUX4 (Z, D0, D1, D2, D3, A, B);
    output Z;
    input D0, D1, D2, D3, A, B;
wire abar, bbar, z1, z2, z3, z4;

    // FUNCTION: 4:1 MUX

not i6 (abar, A);
not i7 (bbar, B);
nand i1 (z1, bbar, abar, D0);
nand i2 (z2, bbar, A, D1);
nand i3 (z3, B, abar, D2);
nand i4 (z4, B, A, D3);
nand i5 (Z, z1, z2, z3, z4);

endmodule

//
// Verilog Simulation model for GTECH_MUX4 //

module GTECH_MUX4(D0,D1,D2,D3,A,B,Z);
input	D0,D1,D2,D3,A,B;
output	Z;

        GTECH_UDP_MUX4 U1 (Z_int, D0, D1, D2, D3, A, B);
        buf  (Z, Z_int);
endmodule
//
// Verilog Simulation model for GTECH_MUX8 //

module GTECH_MUX8(D0,D1,D2,D3,D4,D5,D6,D7,A,B,C,Z);
input	D0,D1,D2,D3,D4,D5,D6,D7,A,B,C;
output	Z;

        GTECH_UDP_MUX4 U1 (D1_int, D0, D1, D2, D3, A, B);
        GTECH_UDP_MUX4 U2 (D2_int, D4, D5, D6, D7, A, B);
        GTECH_UDP_MUX2 U3 (Z_int, D1_int, D2_int, C);
        buf  (Z, Z_int);

endmodule
//
// Verilog Simulation model for GTECH_MUXI2 //

module GTECH_MUXI2(A,B,S,Z);
input	A,B,S;
output	Z;
       
        GTECH_UDP_MUX2 U1 (Z_int, A, B, S);
        not  (Z, Z_int);
endmodule
//
// Verilog Simulation model for GTECH_NAND2 //

module GTECH_NAND2(A,B,Z);
input	A,B;
output	Z;
nand		U(Z,A,B);
endmodule
//
// Verilog Simulation model for GTECH_NAND3 //

module GTECH_NAND3(A,B,C,Z);
input	A,B,C;
output	Z;
nand		U(Z,A,B,C);
endmodule
//
// Verilog Simulation model for GTECH_NAND4 //

module GTECH_NAND4(A,B,C,D,Z);
input	A,B,C,D;
output	Z;
nand		U(Z,A,B,C,D);
endmodule
//
// Verilog Simulation model for GTECH_NAND5 //

module GTECH_NAND5(A,B,C,D,E,Z);
input	A,B,C,D,E;
output	Z;
nand		U(Z,A,B,C,D,E);
endmodule
//
// Verilog Simulation model for GTECH_NAND8 //

module GTECH_NAND8(A,B,C,D,E,F,G,H,Z);
input	A,B,C,D,E,F,G,H;
output	Z;
nand		U(Z,A,B,C,D,E,F,G,H);
endmodule
//
// Verilog Simulation model for GTECH_NOR2 //

module GTECH_NOR2(A,B,Z);
input	A,B;
output	Z;
nor		U(Z,A,B);
endmodule
//
// Verilog Simulation model for GTECH_NOR3 //

module GTECH_NOR3(A,B,C,Z);
input	A,B,C;
output	Z;
nor		U(Z,A,B,C);
endmodule
//
// Verilog Simulation model for GTECH_NOR4 //

module GTECH_NOR4(A,B,C,D,Z);
input	A,B,C,D;
output	Z;
nor		U(Z,A,B,C,D);
endmodule
//
// Verilog Simulation model for GTECH_NOR5 //

module GTECH_NOR5(A,B,C,D,E,Z);
input	A,B,C,D,E;
output	Z;
nor		U(Z,A,B,C,D,E);
endmodule
//
// Verilog Simulation model for GTECH_NOR8 //

module GTECH_NOR8(A,B,C,D,E,F,G,H,Z);
input	A,B,C,D,E,F,G,H;
output	Z;
nor		U(Z,A,B,C,D,E,F,G,H);
endmodule
//
// Verilog Simulation model for GTECH_NOT //

module GTECH_NOT(A,Z);
input	A;
output	Z;
not		U(Z,A);
endmodule
//
// Verilog Simulation model for GTECH_OA21 //

module GTECH_OA21(A,B,C,Z);
input	A,B,C;
output	Z;
wire	AB;
or			U1(AB,A,B);
and		U2(Z,AB,C);
endmodule
//
// Verilog Simulation model for GTECH_OA22 //

module GTECH_OA22(A,B,C,D,Z);
input	A,B,C,D;
output	Z;
wire	AB,CD;
or			U1(AB,A,B);
or			U2(CD,C,D);
and		U3(Z,AB,CD);
endmodule
//
// Verilog Simulation model for GTECH_OAI21 //

module GTECH_OAI21(A,B,C,Z);
input	A,B,C;
output	Z;
wire	AB;
or			U1(AB,A,B);
nand		U2(Z,AB,C);
endmodule
//
// Verilog Simulation model for GTECH_OAI22 //

module GTECH_OAI22(A,B,C,D,Z);
input	A,B,C,D;
output	Z;
wire	AB,CD;
or			U1(AB,A,B);
or			U2(CD,C,D);
nand		U3(Z,AB,CD);
endmodule
//
// Verilog Simulation model for GTECH_OAI2N2 //

module GTECH_OAI2N2(A,B,C,D,Z);
input	A,B,C,D;
output	Z;
wire	AB,CD;
or			U1(AB,A,B);
nand			U2(CD,C,D);
nand		U3(Z,AB,CD);
endmodule
//
// Verilog Simulation model for GTECH_ONE //

module GTECH_ONE(Z);
output	Z;
wire	Z;
assign	Z = 1'b1;
endmodule
//
// Verilog Simulation model for GTECH_OR2 //

module GTECH_OR2(A,B,Z);
input	A,B;
output	Z;
or		U(Z,A,B);
endmodule
//
// Verilog Simulation model for GTECH_OR3 //

module GTECH_OR3(A,B,C,Z);
input	A,B,C;
output	Z;
or		U(Z,A,B,C);
endmodule
//
// Verilog Simulation model for GTECH_OR4 //

module GTECH_OR4(A,B,C,D,Z);
input	A,B,C,D;
output	Z;
or		U(Z,A,B,C,D);
endmodule
//
// Verilog Simulation model for GTECH_OR5 //

module GTECH_OR5(A,B,C,D,E,Z);
input	A,B,C,D,E;
output	Z;
or		U(Z,A,B,C,D,E);
endmodule
//
// Verilog Simulation model for GTECH_OR8 //

module GTECH_OR8(A,B,C,D,E,F,G,H,Z);
input	A,B,C,D,E,F,G,H;
output	Z;
or		U(Z,A,B,C,D,E,F,G,H);
endmodule
//
// Verilog Simulation model for GTECH_OR_NOT //

module GTECH_OR_NOT(A,B,Z);
input	A,B;
output	Z;
wire	BN;
not			U1(BN,B);
or		U2(Z,A,BN);
endmodule
//
// Verilog Simulation model for GTECH_OUTBUF //

module GTECH_OUTBUF(DATA_OUT,OE,PAD_OUT);
input	DATA_OUT,OE;
output	PAD_OUT;
assign	 PAD_OUT = OE? (DATA_OUT & 1'b1) : 1'bz;
endmodule
//
// Verilog Simulation model for GTECH_TBUF //

module GTECH_TBUF(A,E,Z);
input   A,E;
output  Z;
bufif1  U1 ( Z,A,E);
endmodule
//
// Verilog Simulation model for GTECH_XNOR2 //

module GTECH_XNOR2(A,B,Z);
input	A,B;
output	Z;
xnor		U(Z,A,B);
endmodule
//
// Verilog Simulation model for GTECH_XNOR3 //

module GTECH_XNOR3(A,B,C,Z);
input	A,B,C;
output	Z;
xnor		U(Z,A,B,C);
endmodule
//
// Verilog Simulation model for GTECH_XNOR4 //

module GTECH_XNOR4(A,B,C,D,Z);
input	A,B,C,D;
output	Z;
xnor		U(Z,A,B,C,D);
endmodule
//
// Verilog Simulation model for GTECH_XOR2 //

module GTECH_XOR2(A,B,Z);
input	A,B;
output	Z;
xor		U(Z,A,B);
endmodule
//
// Verilog Simulation model for GTECH_XOR3 //

module GTECH_XOR3(A,B,C,Z);
input	A,B,C;
output	Z;
xor		U(Z,A,B,C);
endmodule
//
// Verilog Simulation model for GTECH_XOR4 //

module GTECH_XOR4(A,B,C,D,Z);
input	A,B,C,D;
output	Z;
xor		U(Z,A,B,C,D);
endmodule
//
// Verilog Simulation model for GTECH_ZERO //

module GTECH_ZERO(Z);
output	Z;
wire	Z;
assign	Z = 1'b0;
endmodule