References

1

D. Adler. A Parallel Switch-Level Circuit Simulator. Master's thesis, Rutgers University, ECE Dept., Oct. 1990.

2

P. Agrawal, V.D. Agrawal, M.L. Bushnell, and J. Sienicki. Superlinear Speedup in a Multiprocessing Environment. In Proceedings of the International Workshop on Parallel Processing, Dec. 1994.

3

D. Brasen. Full-Custom Macro Cell Floorplanning and Placement Under Timing Constraints Processor. Master's thesis, Rutgers University, ECE Dept., Oct. 1989.

4

D. Brasen and M. L. Bushnell. MHERTZ: A New Optimization Algorithm for Floorplanning and Global Routing. In Proceedings of the 27th Design Automation Conference, pages 107-110. ACM/IEEE, June 1990.

5

M. L. Bushnell. DELILAH II - An Enhanced Menu-Driven Input Processor. Master's thesis, Carnegie Mellon University, ECE Dept., Feb. 1983.

6

M. L. Bushnell. ULYSSES - An Expert-System Based VLSI Design Environment. PhD thesis, Carnegie Institute of Technology, Carnegie-Mellon University, ECE Dept., Oct. 1986.

7

M. L. Bushnell. Design Automation. Academic Press Perspectives in Computing Series, 1988.

8

M. L. Bushnell. Rapid Application-Specific Electronic Module Design and Test. In Proceedings of the Defense Advanced Research Projects Agency Application-Specific Electronic Modules Conference, U.S. Dept. of Defense, IBM, Poughkeepsie, New York., Sept. 1994.

9

M. L. Bushnell. Rapid Application-Specific Electronic Module Design and Test. In Proceedings of the Defense Advanced Research Projects Agency Electronic Packaging and Interconnect Meeting (EPI), U.S. Dept. of Defense, Marina Del Ray, California., Feb. 1994.

10

M. L. Bushnell. Built-In and External Test of Known Good Die for Mixed Signal Modules. In Proceedings of the Electronic Packaging and Interconnects Conference, Defense Advanced Research Projects Agency, U.S. Dept. of Defense, Herndon, Virginia, April-May 1996.

11

M. L. Bushnell. Future Directions in Sequential Automatic Test-Pattern Generation. In Proceedings of the IEEE Computer Society 1996 Annual Workshop on VLSI, Nov. 1996. Invited paper.

12

M. L. Bushnell and S. W. Director. ULYSSES - An Expert-System Based VLSI Design Environment. In Proceedings of the International Symposium on Circuits and Systems, pages 893-896, June 1985.

13

M. L. Bushnell and S. W. Director. VLSI CAD Tool Integration Using the Ulysses Environment. In Proceedings of the 23rd Design Automation Conference, pages 55-61. ACM/IEEE, June-July 1986.

14

M. L. Bushnell and S. W. Director. ULYSSES - A Knowledge Based VLSI Design Environment. International Journal for Artificial Intelligence in Engineering, 2(1):34-41, Jan. 1987.

15

M. L. Bushnell and S. W. Director. Automated Design Tool Execution in the Ulysses Design Environment. IEEE Transactions on Computer-Aided Design, 8(3):279-287, March 1989.

16

M. L. Bushnell and J. Giraldi. A Functional Decomposition Method for Redundancy Identification and Test Generation. Journal of Electronic Testing: Theory and Applications, 10(3):175-195, June 1997.

17

M. L. Bushnell and D. H. Howling. Tutorial Paper on Programming Languages. In Proceedings of the Instrument Society of America Gordon Conference, Geneva, New York, July 1980.

18

M. L. Bushnell and J. J. Martin. Computerized Thermal Mechanical Fatigue Testing. Industrial Research, 19(7):60-64, July 1977.

19

M. L. Bushnell and I. P. Shaik. Robust Delay Fault Built-In Self-Testing Method and Apparatus. U.S. Patent # 5,422,891, issued 6/6/95.

20

M. L. Bushnell and L. K. Sisterson. A Software Driver for a Real-Time Laboratory Automation System. In B. C. Wonsiewicz, editor, Computer Automation of Materials Testing, pages 26-47. Special Technical Publication 710, American Society for Testing and Materials, Philadelphia., Philadelphia, Pa., Nov. 1980.

21

T. J. Chakraborty. Delay Fault Test-Pattern Generation for Random Logic State Machines. PhD thesis, Rutgers University, ECE Dept., Oct. 1993.

22

T. J. Chakraborty, V. D. Agrawal, and M. L. Bushnell. Delay Fault Testing for Random Logic Sequential Circuits. In Proceedings of the 29th Design Automation Conference, pages 165-172. ACM/IEEE, June 1992.

23

T. J. Chakraborty, V. D. Agrawal, and M. L. Bushnell. New Methods for Delay Fault Testing of Sequential Circuits. In Proceedings of the 11th AT&T Conference on Electronic Testing, Oct. 1992.

24

T. J. Chakraborty, V. D. Agrawal, and M. L. Bushnell. Path Delay Fault Simulation Algorithms for Sequential Circuits. In Proceedings of the 1992 Asian Test Symposium, pages 51-56, Nov. 1992.

25

T. J. Chakraborty, V. D. Agrawal, and M. L. Bushnell. Design for Testability for Path Delay Faults in Sequential Circuits. In Proceedings of the 30th Design Automation Conference, pages 453-457. ACM/IEEE, June 1993.

26

T. J. Chakraborty, V. D. Agrawal, and M. L. Bushnell. On a Variable Clock Method for Path Delay Testing of Sequential Circuits. IEEE Transactions on Computer-Aided Design, 16(11):1237-1249, Nov. 1997.

27

T. J. Chakraborty, M. L. Bushnell, and V. D. Agrawal. Improving Path Delay Testability of Sequential Circuits. IEEE Transactions on VLSI Systems, 1998. Submitted.

28

S. T. Chakradhar, V. D. Agrawal, and M. L. Bushnell. Automatic Test Generation Using Neural Networks. In Proceedings of the International Conference on Computer-Aided Design, pages 416-419, Nov. 1988.

29

S. T. Chakradhar, V. D. Agrawal, and M. L. Bushnell. Automatic Test Generation Using Quadratic 0-1 Programming. In Proceedings of the 27th Design Automation Conference, pages 654-659. ACM/IEEE, June 1990. One of 15 papers nominated for a Best Paper Award.

30

S. T. Chakradhar, V. D. Agrawal, and M. L. Bushnell. Polynomial Time Solvable Fault Detection Problems. In Proceedings of the International Fault-Tolerant Computing Symposium, pages 56-63, June 1990.

31

S. T. Chakradhar, V. D. Agrawal, and M. L. Bushnell. Energy Minimization Solution of VLSI Test Generation. In The Institute of Management Science/Operations Research Society of America Joint National Meeting, Chicago, May 1993. Sponsored Paper.

32

S. T. Chakradhar and M. L. Bushnell. A Solvable Class of Quadratic 0-1 Programming. Journal of Discrete Applied Mathematics, 36(3):233-251, May 1992.

33

S. T. Chakradhar, M. L. Bushnell, and V. D. Agrawal. Neural Net and Boolean Satisfiability Models of Logic Circuits. IEEE Design & Test of Computers, 7(5):54-57, Oct. 1990.

34

S. T. Chakradhar, M. L. Bushnell, and V. D. Agrawal. Toward Massively Parallel Automatic Test Generation. IEEE Transactions on Computer-Aided Design, 9(9):981-994, Sept. 1990. Also issued as AT&T Bell Laboratories Technical Memorandum # 11273-900814-03TM.

35

S. T. Chakradhar, M. L. Bushnell, and V. D. Agrawal. Test Generation Using Neural Computers. International Journal of Computer-Aided VLSI Design, 3(3):241-257, 1991. Also issued as AT&T Bell Laboratories Technical Memorandum # 11273-900816-07TM.

36

S. T. Chakradhar, M. L. Bushnell, and V. D. Agrawal. Energy Minimization and Design for Testability. Journal of Electronic Testing: Theory and Applications, 5(1):57-66, Feb. 1994. Also issued as AT&T Bell Laboratories Technical Memorandum # 11273-900814-05TM.

37

S.T. Chakradhar. Neural Network Models for Test-Pattern Generation. PhD thesis, Rutgers University, CS Dept., May 1990.

38

S.T. Chakradhar, V.D. Agrawal, and M.L. Bushnell. Neural Models and Algorithms for Digital Testing. Kluwer Academic Publishers, 1991.

39

A. Chang. An Implementation of Constrained Quadratic 0-1 Programming for Automatic Test Pattern Generation for VLSI Circuits. Master's thesis, Rutgers University, ECE Dept., May 1992.

40

X. Chen. Full-Custom Layout Area and Aspect Ratio Estimation. Master's thesis, Rutgers University, ECE Dept., May 1988.

41

X. Chen. State and Objective Learning for Sequential Circuit Automatic Test Pattern Generation. PhD thesis, Rutgers University, ECE Dept., Oct. 1993.

42

X. Chen and M. L. Bushnell. A Module Area Estimator for VLSI Layout. In Proceedings of the 25th Design Automation Conference, pages 54-59. ACM/IEEE, June 1988.

43

X. Chen and M. L. Bushnell. Dynamic State and Objective Learning for Sequential Automatic Test-Pattern Generation. In Proceedings of the International Fault-Tolerant Computing Symposium, pages 446-455, June 1994.

44

X. Chen and M. L. Bushnell. Efficient Branch and Bound Search with Application to Computer Aided Design. Kluwer Academic Publishers, Nov. 1995.

45

X. Chen and M. L. Bushnell. Sequential Circuit Test Generation Using Dynamic Justification Equivalence. Journal of Electronic Testing: Theory and Applications, 8(1):9-34, Feb. 1996.

46

X. Chen and M.L. Bushnell. MAE - A Module Area Estimator for VLSI Layout. Technical Report CAIP-SR-007, CAIP Center, Rutgers University, Sept. 1988.

47

X. Chen and M.L. Bushnell. Justification State Equivalence for Sequential Circuit Automatic Test Generation. Technical Report CAIP-TR-173, CAIP Center, Rutgers University, Nov. 1993.

48

X. Chen and M.L. Bushnell. Generalization of Search State Equivalence for Automatic Test Pattern Generation. Technical Report CAIP-TR-191, CAIP Center, Rutgers University, Aug. 1994.

49

X. Chen and M.L. Bushnell. Generalization of Search State Equivalence for Automatic Test Pattern Generation. In Proceedings of the 8th International Conference on VLSI Design, pages 99-103, Jan. 1995.

50

C. Cooper. Automatic Switch-Level Test Generation Using Energy Minimization. Master's thesis, Rutgers University, ECE Dept., Jan. 1994.

51

C. Cooper and M. L. Bushnell. Neural Models for Mixed-Level Test Generation. In Proceedings of the 12th VLSI Test Symposium, pages 208-213. IEEE, April 1994.

52

C. Cooper and M. L. Bushnell. Switch-Level Automatic Test Generation Using Graph Methods. In The Institute of Management Science/Operations Research Society of America Joint National Meeting, Anchorage, Alaska, June 1994. Invited paper.

53

M.A. Gharabyeh, V.D. Agrawal, and M. L. Bushnell. False-Path Removal Using Delay Fault Simulation. In Proceedings of the 1998 Asian Test Symposium, 1998. Submitted.

54

M. Gharaybeh. On Testing High-Speed Digital VLSI Circuits. PhD thesis, Rutgers University, ECE Dept., July 1996.

55

M. A. Gharaybeh, V. D. Agrawal, and M. L. Bushnell. Classification and Test Generation for Path-Delay Faults Using Single Stuck-Fault Tests. In Proceedings of the International Test Conference, pages 139-148. IEEE, Oct. 1995.

56

M. A. Gharaybeh, M. L. Bushnell, and V. D. Agrawal. An Exact Non-Enumerative Fault Simulator for Path-Delay Faults. U.S. Patent Application, Filed 10/23/97.

57

M. A. Gharaybeh, M. L. Bushnell, and V. D. Agrawal. Classification and Test Generation for Path-Delay Faults via Single Stuck-Fault Test Generation. In International Test Synthesis Workshop, May 1995.

58

M. A. Gharaybeh, M. L. Bushnell, and V. D. Agrawal. An Exact Non-Enumerative Fault Simulator for Path-Delay Faults. In Proceedings of the International Test Conference, pages 276-285. IEEE, Oct. 1996.

59

M. A. Gharaybeh, M. L. Bushnell, and V. D. Agrawal. An Exact Non-Enumerative Fault Simulator for Path-Delay Faults. In Proceedings of TECHCON '96, Sept. 1996. Phoenix, Arizona, Semiconductor Research Corporation.

60

M. A. Gharaybeh, M. L. Bushnell, and V. D. Agrawal. Parallel Concurrent Path-Delay Fault Simulation Using Single-Input Change Patterns. In Proceedings of the 9th International Conference on VLSI Design, pages 426-431, Jan. 1996.

61

M. A. Gharaybeh, M. L. Bushnell, and V. D. Agrawal. Classification and Test Generation for Path-Delay Faults Using Single Stuck-at Fault Tests. Journal of Electronic Testing: Theory and Applications, 11(1):55-68, Aug. 1997.

62

M. A. Gharaybeh, M. L. Bushnell, and V. D. Agrawal. A Parallel-Vector Concurrent-Fault Simulator and Generation of Single-Input Change Tests for Path Delay Faults. IEEE Transactions on Computer-Aided Design, 1998. Accepted.

63

M. A. Gharaybeh, M. L. Bushnell, and V. D. Agrawal. The Path Status Graph with Application to Delay Fault Simulation. IEEE Transactions on Computer-Aided Design, 1998. Accepted.

64

P. Ghosh. Transistor Stuck-Open Fault Test Generation for Switch-Level Circuits Using Energy Minimization Techniques. Master's thesis, Rutgers University, ECE Dept., May 1996.

65

J. Giraldi. Heuristic Algorithms for Combinational Automatic Test-Pattern Generation. PhD thesis, Rutgers University, ECE Dept., Oct. 1990.

66

J. Giraldi and M. L. Bushnell. EST: The New Frontier in Automatic Test Pattern Generation. In Proceedings of the 27th Design Automation Conference, pages 667-672. ACM/IEEE, June 1990.

67

J. Giraldi and M. L. Bushnell. Search State Equivalence for Redundancy Identification and Test Generation. In Proceedings of the International Test Conference, pages 184-193. IEEE, Oct. 1991.

68

K. Heragu. Approximate and Statistical Methods to Compute Delay Fault Coverage. Master's thesis, Rutgers University, ECE Dept., May 1994.

69

K. Heragu, V. D. Agrawal, and M. L. Bushnell. An Efficient Path Delay Coverage Estimator. In Proceedings of the 31st Design Automation Conference, pages 516-521. ACM/IEEE, June 1994.

70

K. Heragu, V. D. Agrawal, and M. L. Bushnell. FACTS: Fault Coverage Estimation by Test Vector Sampling. In Proceedings of the 12th VLSI Test Symposium, pages 266-271. IEEE, April 1994.

71

K. Heragu, V. D. Agrawal, and M. L. Bushnell. Statistical Methods for Delay Fault Coverage Analysis. In Proceedings of the 8th International Conference on VLSI Design, pages 166-170, Jan. 1995.

72

K. Heragu, V. D. Agrawal, M. L. Bushnell, and J. H. Patel. Improving a Non-Enumerative Method to Estimate Path Delay Fault Coverage. IEEE Transactions on Computer-Aided Design, 16(7):759-761, July 1997.

73

K. Heragu, M. L. Bushnell, and V. D. Agrawal. Fault Coverage Estimation by Test Vector Sampling. IEEE Transactions on Computer-Aided Design, 14(5):590-596, May 1995.

74

M. Iyer. Effect of Noise on Analog Circuit Testing. Master's thesis, Rutgers University, ECE Dept., Jan. 1998.

75

M. Iyer and M. L. Bushnell. Effect of Noise on Analog Circuit Testing. In Proceedings of the 16th VLSI Test Symposium, pages 138-144. IEEE, April 1998.

76

S. M. Komar, M. L. Bushnell, and V. D. Agrawal. Functional Test Generation for Path Delay Faults. In Proceedings of the 1995 Asian Test Symposium, pages 339-345, Nov. 1995.

77

S. M. Komar, M. L. Bushnell, and V. D. Agrawal. Flags and Algebra for Sequential Circuit VNR Path Delay Fault Test Generation. In Proceedings of the 10th International Conference on VLSI Design, pages 88-94, Jan. 1997.

78

D. P. LaPotin, S. R. Nassif, M. L. Bushnell, J. V. Rajan, and J. A. Nestor. DIF: A Framework for VLSI Multi-Level Representation. INTEGRATION, the VLSI Journal, 2(3):227-241, Sept. 1984.

79

Q. Lin. Efficient Techniques for a Transitive Closure-Based Test Generation Algorithm. Master's thesis, Rutgers University, ECE Dept., Jan. 1996.

80

Q. Lin and M. L. Bushnell. Decision Heuristics for Accelerated Automatic Test Generation Using Hopfield Neural Net Models. In Proceedings of the 1994 Joint Conference on Information Sciences, Pinehurst, North Carolina, Nov. 1994. Invited paper.

81

Q. Lin, M. L. Bushnell, and V. D. Agrawal. Redundancy Identification Using Transitive Closure. Third International Test Synthesis Workshop, May 1996.

82

Q. Lin, M. L. Bushnell, and V. D. Agrawal. Redundancy Identification Using Transitive Closure. In Proceedings of the Fifth Asian Test Symposium, pages 4-9, Nov. 1996.

83

S. Majumder, V. D. Agrawal, and M. L. Bushnell. On Delay-Untestable Paths and Stuck-Fault Redundancy. In Proceedings of the 16th VLSI Test Symposium, pages 194-199. IEEE, April 1998.

84

S. Majumder, V. D. Agrawal, and M. L. Bushnell. Path Delay Testing: Variable-Clock Versus Rated-Clock. In Proceedings of the 11th International Conference on VLSI Design, pages 470-475, Jan. 1998.

85

L. Pappu, M. L. Bushnell, and V. D. Agrawal. Markov Chain Based Sequential Automatic Test Pattern Generator. Third International Test Synthesis Workshop, May 1997.

86

L. Pappu, M. L. Bushnell, V. D. Agrawal, and S. M. Komar. Statistical Path-Delay Fault Coverage Estimation for Sequential Synchronous Circuits. In Proceedings of the 9th International Conference on VLSI Design, pages 290-295, Jan. 1996.

87

L. Pappu, M. L. Bushnell, V. D. Agrawal, and M. K. Srinivas. Statistical Delay Fault Coverage Estimation for Synchronous Sequential Circuits. Journal of Electronic Testing: Theory and Applications, 1998. Accepted.

88

S. Parikh. Automatic CAD Tool Execution in the Ulysses II CAD Framework. Master's thesis, Rutgers University, ECE Dept., Oct. 1992.

89

S. Parikh, M. L. Bushnell, R. Ganesh, and J. Sienicki. Distributed Computing, Automatic Design, and Error Recovery in the Ulysses II Framework. In Proceedings of theEuropean Design and Test Conference, pages 610-617, Feb. 1994.

90

C. G. Parodi, V. D. Agrawal, M. L. Bushnell, and S. Wu. A Non-Enumerative Path Delay Fault Simulator for Sequential Circuits. In Proceedings of the International Test Conference. IEEE, 1998. Accepted.

91

G. Parthasarathy. Delay Fault Built-In Self-Test and Partial-Scan Insertion for Sequential Circuits. Master's thesis, Rutgers University, ECE Dept., Jan. 1998.

92

G. Parthasarathy and M. L. Bushnell. Simultaneous Delay-Fault Built-In Self-Test and Partial-Scan Insertion. U.S. Provisional Patent Application # 98-0081, 3/2/98.

93

G. Parthasarathy and M. L. Bushnell. Towards Simultaneous Delay-Fault Built-In Self-Test and Partial-Scan Insertion. In Proceedings of the 16th VLSI Test Symposium, pages 210-217. IEEE, April 1998.

94

R. Ramadoss. Test Generation for Mixed-Signal Devices Using Signal Flow Graphs. Master's thesis, Rutgers University, ECE Dept., Feb. 1996.

95

R. Ramadoss and M. L. Bushnell. U.S. Patent App. # 08/582,365, Test Generation for Mixed-Signal Devices Using Signal Flow Graphs. Filed Jan. 5, 1996.

96

R. Ramadoss and M. L. Bushnell. Test Generation for Mixed-Signal Devices Using Signal Flow Graphs. In Proceedings of the 9th International Conference on VLSI Design, pages 242-248, Jan. 1996. Winner of the Honorable Mention Award.

97

R. Ramadoss and M. L. Bushnell. Flash A/D Converters - Design for Testability. In Proceedings of the Mixed-Signal Test Workshop, June 1997.

98

R. Ramadoss and M. L. Bushnell. Test Generation for Analog Circuits Using Partitioning and Inverted System Simulation. In Proceedings of the Mixed-Signal Test Workshop, June 1998.

99

R. Ramadoss and M. L. Bushnell. Test Generation for Mixed-Signal Devices Using Signal Flow Graphs. Journal of Electronic Testing: Theory and Applications, 1998. Submitted.

100

R. Ramadoss, M. L. Bushnell, and V. D. Agrawal. Minimum Observable Signal Variation: A New Mixed-Signal Fault Model. In Proceedings of the Mixed-Signal Test Workshop, June 1997.

101

I. Shaik and M. L. Bushnell. A Graph Approach to DFT Hardware Placement for Robust Delay-Fault BIST. In Proceedings of the 8th International Conference on VLSI Design, pages 177-182, Jan. 1995.

102

I. P. Shaik and M. L. Bushnell. A Graphical Approach to Circuit Cut-Point Placement for Design for Testability. Invited paper., August 1994.

103

I. P. Shaik and M. L. Bushnell. Circuit Design for Low Overhead Delay-Fault BIST Using Constrained Quadratic 0-1 Programming. In Proceedings of the 13th VLSI Test Symposium, pages 393-399. IEEE, April 1995.

104

I.P. Shaik. Robust Built-In Self-Testing for Circuit Delay Faults. Master's thesis, Rutgers University, ECE Dept., May 1993.

105

I.P. Shaik. Robust Built-In Self-Testing for Combinational Circuit Delay Faults. PhD thesis, Rutgers University, ECE Dept., June 1996.

106

I.P. Shaik and M.L. Bushnell. Automatic Circuit Redesign for Delay Fault Testability Using Constrained Quadratic 0-1 Programming. In Proceedings of the 15th Int'l Symposium on Mathematical Programming, Aug. 1994.

107

J. Sienicki. Graphical Methodology Language for CAD Frameworks. Master's thesis, Rutgers University, ECE Dept., Oct. 1992.

108

J. Sienicki. Super-Linear Speedup in Distributed Test Generation Algorithms. PhD thesis, Rutgers University, ECE Dept., Oct. 1995.

109

J. Sienicki, P. Agrawal, V. D. Agrawal, and M. L. Bushnell. Superlinear Speedup in Multiprocessing Environment. In Proceedings of the First International Workshop on Parallel Processing, pages 261-265, Dec. 1994.

110

J. Sienicki, P. Agrawal, V.D. Agrawal, and M. Bushnell. Distributed Gentest. In Proceedings of the AT&T Conference on Electronic Test, pages 285-294, Sept. 1993.

111

J. Sienicki, P. Agrawal, M. L. Bushnell, and V. D. Agrawal. An Adaptive Distributed Algorithm for Sequential Circuit Test Generation. In Proceedings of the European Design Automation Conference, pages 236-241, Sept. 1995.

112

J. Sienicki and M. L. Bushnell. Graphical Methodology Language for CAD Frameworks. In Proceedings of the 7th International Conference on VLSI Design, pages 401-406, Jan. 1994.

113

J. Sienicki, M. L. Bushnell, P. Agrawal, and V. D. Agrawal. An Asynchronous Algorithm for Sequential Circuit Test Generation on a Network of Workstations. In Proceedings of the 8th International Conference on VLSI Design, pages 36-41, Jan. 1995. Nominated for a Best Paper Award.

114

J. Sienicki, M. L. Bushnell, P. Agrawal, and V. D. Agrawal. Sequential Circuit Test Generation on a Network of Workstations. IEEE Transactions on Computer-Aided Design, 1998. Under revision.

115

J. Sienicki and M.L. Bushnell. A Graphical Methodology Language for CAD Frameworks. In Proceedings of the 7th International Conference on VLSI Design, pages 401-406, Jan. 1994.

116

J. Sienicki, M.L. Bushnell, P. Agrawal, and V.D. Agrawal. An Asynchronous Algorithm for Sequential Circuit Test Generation. In Proceedings of the AT&T Conference on Electronic Test, April 1995.

117

J. Williams. K-Tree Circuit Partitioning. Master's thesis, Rutgers University, ECE Dept., Oct. 1992.

118

J. Williams and M. L. Bushnell. K-Tree Circuit Partitioning. In The Institute of Management Science/Operations Research Society of America Joint National Meeting, Chicago, May 1993. Sponsored Paper.