Table of Contents
BUILT-IN AND EXTERNAL TEST OF KNOWN GOOD DIE FOR MIXED SIGNAL MODULES
Michael L. Bushnell -- Rutgers University
OBJECTIVES AND MAIN TECHNICAL APPROACH
MAJOR TECHNICAL ACCOMPLISHMENTS SINCE LAST REVIEW
TECHNOLOGY IMPACT / TRANSITION PLAN
PARTIAL-SCAN DELAY-FAULT BUILT-IN SELF-TEST OF LARGE CIRCUITS
OR HOW TO DO MORE WITH LESS
OBJECTIVE
APPROACH
APPROACH
WHAT IS PATH DELAY TESTING?
CYCLE CUTTING / PARITY FLIPPING TO ELIMINATE HAZARDS
FULL SCAN AND PARTIAL-SCAN FLIP-FLOPS
SEQUENTIAL CKT. HARDWARE CONFIGURATION
c17 --> WEIGHTED SIGNED GRAPH
LOGIC GATES IN 1989 ISCAS CIRCUITS
HARDWARE CHIP AREA OVERHEAD COMPONENTS
TOTAL HARDWARE CHIP AREA OVERHEAD
ABSOLUTE CHIP AREA OVERHEAD COMPONENTS
CPU TIMES ON 150 MHERTZ SPARC STATION 20
TRANSITION DELAY FAULT COVERAGE
PATH DELAY FAULT COVERAGES ON ISCAS 89 CIRCUITS
TESTABILITY INSERTION
ADVANTAGES
FUTURE WORK
|
Author: CAIP Center
Email: bushnell@caip.rutgers.edu
Home Page: http://www-caip.rutgers.edu/~bushnell/rutgers.html
|