Authors: Michael L. Bushnell and Vishwani D. Agrawal

The Second Printing is now available from Kluwer Academic Publishers.

Cover (jpg) / Table of Contents (postscript or pdf) / Preface (postscript or pdf)
Bibliography (postscript or pdf) / Index (postscript or pdf)
CORRECTIONS (applicable only to First Printing)
Available now: How to order

VLSI Testing Course (all Powerpoint Slides and course materials can be downloaded by anyone):

Syllabus (4 pages) / postscript / pdf
Homework Assignments
Class Projects
Rutgers Modeling Language (rutmod) User's Manual (14 pages) / postscript / pdf
Lecture 1: Introduction (powerpoint, 16 slides)
Lecture 2: Test Process and ATE (powerpoint, 43 slides)
Lecture 3: Test Economics (powerpoint, 16 slides)
Lecture 4: Yield Analysis & Product Quality (powerpoint, 15 slides)
Lecture 5: Fault Modeling (powerpoint, 18 slides)
Lecture 6: Logic Simulation (powerpoint, 15 slides)
Lecture 7: Fault Simulation (powerpoint, 20 slides)
Lecture 8: Testability Measures (powerpoint, 36 slides)
Lecture 9: Combinational ATPG Basics (powerpoint, 26 slides)
Lecture 10: Redundancy Removal using ATPG (powerpoint, 9 slides)
Lecture 11: Major Combinational ATPG Algorithms (powerpoint, 71 slides)
Lecture 12: Advanced Combinational ATPG Algorithms (powerpoint, 57 slides)
Lecture 13: Seq. Circuit ATPG - Time-Frame Expansion (powerpoint, 22 slides)
Lecture 14: Seq. Circuit ATPG - Simulation-Based Methods (powerpoint, 25 slides)
Lecture 15: Memory Test (powerpoint, 65 slides)
Lecture 16: Pattern Sensitive and Electrical Memory Test (powerpoint, 33 slides)
Lecture 17: Analog Circuit Test - A/D and D/A Converters (powerpoint, 34 slides)
Lecture 18: DSP-Based Analog Circuit Testing (powerpoint, 57 slides)
Lecture 19: Fault Model Based Structural Analog Testing (powerpoint, 22 slides)
Lecture 20: Delay Test (powerpoint, 25 slides)
Lecture 21: IDDQ Current Testing (powerpoint, 39 slides)
Lecture 22: Delta-IDDQ Testing and Built-In Current Testing (powerpoint, 18 slides)
Lecture 23: Design for Testability - Full Scan (powerpoint, 22 slides)
Lecture 24: Design for Testability - Partial Scan & Scan Variations (powerpoint, 20 slides)
Lecture 25: BIST Pattern Generation & Response Compaction (powerpoint, 59 slides)
Lecture 26: BIST Architectures (powerpoint, 24 slides)
Lecture 27: Memory and Delay Fault BIST (powerpoint, 24 slides)
Lecture 28: IEEE 1149.1 Boundary Scan Standard (powerpoint, 32 slides)
Lecture 29: Advanced Boundary Scan and BSDL (powerpoint, 21 slides)
Lecture 30: IEEE 1149.4 Analog Bus Standard (powerpoint, 34 slides)
Lecture 31: System Test (powerpoint, 22 slides)

Last modified: Wed Sept. 12, 2001.