14:332:438 Capstone Design -- Computer Systems, VLSI Track, Spring 2008
  The Short Project Requirements have been added to this web site. There is a memo on this web site describing how to use the large color plotter called c633plotter. Sample final project reports and presentations on the web site. For this course, use TSMC 0.18 micron technology, which means use the TSMC 0.2um technology, since the features will be automatically shrunk. Also, the names of the nFET and pFET models for Spectre are TSMC20N and TSMC20P. Welcome back!
Instructor:
Prof. Michael Bushnell (bushnell@caip.rutgers.edu)
Phone: (732) 445-6400 X214
Lecture time: Fri. 3:20-6:20
Classroom: Eng. B-120
Course Laboratories: CORE 601A and CORE 533

Administrative Contact:
Lynn Ruggiero (ruggiero@ece.rutgers.edu)
Phone: (732) 445-5241

Instructions on color plotting: ( word )

Paper on Moore's Law: ( pdf )

Sample Final Project Presentation: ( powerpoint )

Short Project Requirements: ( WORD )

Sample Final Project Writeup: ( word )

Synopsys Operating Instructions: postscript pdf

Cadence Operating Instructions: postscript pdf

Instructions for Using the Verilog Test Generator: postscript / pdf See Mike Bushnell to generate tests.

Instructions for Using the Wavelet Verilog Test Generator: postscript / pdf See Mike Bushnell to generate tests.

Course Syllabus: postscript pdf

Verilog Do's and Don'ts: postscript pdf

Lectures:

• Lecture 1 1/25/2008 Project Team Organization
• Lectures 2-27 2/1/2008 - 4/25/2008 Weekly Individual Project Team Meetings
• Lecture 28 5/2/2007 Final Project Presentations

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Note: Any questions about this site, please email: bushnell@caip.rutgers.edu